Build starting @ 2019-03-05T06:03:38.767272 Running make -C /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid run (with MAKEFLAGS=' -j --jobserver-fds=3,4') --------------------------------------------------------------------------- make[1]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make clean make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' rm -rf build run.ok cd clb && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' cd clb_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' cd iob && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' cd iob_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' cd mmcm && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' cd pll && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' cd ps7_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' cd bram && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' cd bram_block && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' cd bram_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' cd dsp && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' cd dsp_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' cd fifo_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' cd monitor && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' cd monitor_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' cd cfg_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' cd orphan_int_column && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' cd clk_hrow && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' cd clk_bufg && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make database make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' bash generate.sh build/tiles tiles ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate_tiles.tcl # source "$::env(FUZDIR)/util.tcl" ## proc min_ysite { duts_in_column } { ## # Given a list of sites, return the one with the lowest Y coordinate ## ## set min_dut_y 9999999 ## ## foreach dut $duts_in_column { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## if { $dut_y < $min_dut_y } { ## set selected_dut $dut ## set min_dut_y $dut_y ## } ## } ## return $selected_dut ## } ## proc group_dut_cols { duts ypitch } { ## # Group a list of sites into pitch sized buckets ## # Ex: IOBs occur 75 to a CMT column ## # Set pitch to 75 to get 0-74 in one bucket, 75-149 in a second, etc ## # X0Y0 {IOB_X0Y49 IOB_X0Y48 IOB_X0Y47 ... } ## # Anything with a different x is automatically in a different bucket ## ## # LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column) ## set dut_columns "" ## foreach dut $duts { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## # 75 per column => 0, 75, 150, etc ## set y_column [expr ($dut_y / $ypitch) * $ypitch] ## dict append dut_columns "X${dut_x}Y${y_column}" "$dut " ## } ## return $dut_columns ## } ## proc loc_dut_col_bels { dut_columns cellpre cellpost } { ## # set cellpre di ## ## # Pick the smallest Y in each column and LOC a cell to it ## # cells must be named like $cellpre[$dut_index] ## # Return the selected sites ## ## set ret_bels {} ## set dut_index 0 ## ## dict for {column duts_in_column} $dut_columns { ## set sel_bel_str [min_ysite $duts_in_column] ## set sel_bel [get_bels $sel_bel_str] ## if {"$sel_bel" == ""} {error "Bad bel $sel_bel from bel str $sel_bel_str"} ## set sel_site [get_sites -of_objects $sel_bel] ## if {"$sel_site" == ""} {error "Bad site $sel_site from bel $sel_bel"} ## ## set cell [get_cells $cellpre$dut_index$cellpost] ## puts "LOCing cell $cell to site $sel_site (from bel $sel_bel)" ## set_property LOC $sel_site $cell ## ## set dut_index [expr $dut_index + 1] ## lappend ret_bels $sel_bel ## } ## ## return $ret_bels ## } ## proc loc_dut_col_sites { dut_columns cellpre cellpost } { ## set bels [loc_dut_col_bels $dut_columns $cellpre $cellpost] ## set sites [get_sites -of_objects $bels] ## return $sites ## } ## proc make_io_pad_sites {} { ## # get all possible IOB pins ## foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { ## set site [get_sites -of_objects $pad] ## if {[llength $site] == 0} { ## continue ## } ## if [string match IOB33* [get_property SITE_TYPE $site]] { ## dict append io_pad_sites $site $pad ## } ## } ## return $io_pad_sites ## } ## proc make_iob_pads {} { ## set io_pad_sites [make_io_pad_sites] ## ## set iopad "" ## dict for {key value} $io_pad_sites { ## # Some sites have more than one pad? ## lappend iopad [lindex $value 0] ## } ## return $iopad ## } ## proc make_iob_sites {} { ## set io_pad_sites [make_io_pad_sites] ## ## set sites "" ## dict for {key value} $io_pad_sites { ## lappend sites $key ## } ## return $sites ## } ## proc assign_iobs_old {} { ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] ## } ## proc assign_iobs {} { ## # Set all I/Os on the bus to valid values somewhere on the chip ## # The iob fuzzer sets these to more specific values ## ## # All possible IOs ## set iopad [make_iob_pads] ## # Basic pins ## # XXX: not all pads are valid, but seems to be working for now ## # Maybe better to set to XRAY_PIN_* and take out of the list? ## set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb] ## ## # din bus ## set fixed_pins 3 ## set iports [get_ports di*] ## for {set i 0} {$i < [llength $iports]} {incr i} { ## set pad [lindex $iopad [expr $i+$fixed_pins]] ## set port [lindex $iports $i] ## set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port ## } ## } ## proc make_project {} { ## # Generate .bit only over ROI ## make_project_roi XRAY_ROI_TILEGRID ## } ## proc make_project_roi { roi_var } { ## # 6 CMTs in our reference part ## # What is the largest? ## set n_di 16 ## ## create_project -force -part $::env(XRAY_PART) design design ## ## read_verilog "$::env(FUZDIR)/top.v" ## synth_design -top top -verilog_define N_DI=$n_di ## ## assign_iobs ## ## create_pblock roi ## add_cells_to_pblock [get_pblocks roi] [get_cells roi] ## foreach roi "$::env($roi_var)" { ## puts "ROI: $roi" ## resize_pblock [get_pblocks roi] -add "$roi" ## } ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## set_param tcl.collectionResultDisplayLimit 0 ## ## set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] ## } # proc write_tiles_txt {} { # # Get all tiles, ie not just the selected LUTs # set tiles [get_tiles] # # # Write tiles.txt with site metadata # set fp [open "tiles.txt" w] # foreach tile $tiles { # set type [get_property TYPE $tile] # set grid_x [get_property GRID_POINT_X $tile] # set grid_y [get_property GRID_POINT_Y $tile] # set sites [get_sites -quiet -of_objects $tile] # set typed_sites {} # # if [llength $sites] { # set site_types [get_property SITE_TYPE $sites] # foreach t $site_types s $sites { # lappend typed_sites $t $s # } # } # # puts $fp "$type $tile $grid_x $grid_y $typed_sites" # } # close $fp # } # proc run {} { # # Generate grid of entire part # make_project_roi XRAY_ROI_TILEGRID # # place_design # route_design # write_checkpoint -force design.dcp # write_bitstream -force design.bit # # write_tiles_txt # } # run Command: synth_design -top top -verilog_define N_DI=16 Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28432 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 17154 ; free virtual = 51675 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] Parameter DIN_N bound to: 16 - type: integer Parameter DOUT_N bound to: 108 - type: integer INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] INFO: [Synth 8-638] synthesizing module 'roi' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized0' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized1' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized2' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized3' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized4' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized5' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized7' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized7' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized8' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized9' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized9' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized10' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized10' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized11' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized11' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized12' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized12' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized13' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized13' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized14' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized14' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized15' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized15' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized16' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized16' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized17' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized17' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized18' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized18' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized19' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized19' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized20' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized20' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized21' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized21' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized22' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized22' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized23' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized23' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized24' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized24' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized25' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized25' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized26' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized26' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized27' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized27' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized28' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized28' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized29' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized29' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized30' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized30' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized31' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized31' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized32' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized32' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized33' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized33' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized34' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized34' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized35' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized35' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized36' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized36' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized37' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized37' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized38' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized38' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized39' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized39' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized40' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized40' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized41' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized41' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized42' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized42' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized43' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized43' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized44' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized44' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized45' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized45' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized46' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized46' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized47' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized47' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized48' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized48' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized49' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized49' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized50' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized50' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized51' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized51' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized52' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized52' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized53' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized53' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized54' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized54' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized55' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized55' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized56' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized56' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized57' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized57' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized58' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized58' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized59' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized59' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized60' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized60' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized61' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized61' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized62' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized62' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized63' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized63' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized64' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized64' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized65' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized65' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized66' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized66' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized67' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized67' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized68' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized68' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized69' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized69' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized70' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized70' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized71' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized71' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized72' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized72' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized73' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized73' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized74' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized74' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized75' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized75' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized76' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized76' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized77' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized77' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized78' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized78' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized79' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized79' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized80' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized80' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized81' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized81' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized82' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized82' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized83' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized83' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized84' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized84' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized85' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized85' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized86' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized86' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized87' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized87' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized88' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized88' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized89' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized89' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized90' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized90' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized91' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized91' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized92' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized92' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized93' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized93' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized94' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized94' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized95' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized95' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized96' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized96' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized97' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized97' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized98' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized98' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'RAMB36E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized0' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized3' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized4' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized5' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized6' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-256] done synthesizing module 'roi' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-256] done synthesizing module 'top' (5#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] WARNING: [Synth 8-3331] design roi has unconnected port clk --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 17158 ; free virtual = 51681 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 17159 ; free virtual = 51682 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 17159 ; free virtual = 51682 --------------------------------------------------------------------------------- WARNING: [Synth 8-3936] Found unconnected internal register 'din_reg' and it is trimmed from '16' to '8' bits. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:36] INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1205.953 ; gain = 110.508 ; free physical = 17151 ; free virtual = 51674 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (di_bufs[8].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[9].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[10].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[11].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[12].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[13].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[14].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[14]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[13]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[12]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[11]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[10]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[9]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[8]) is unused and will be removed from module top. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.922 ; gain = 233.477 ; free physical = 16989 ; free virtual = 51511 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.922 ; gain = 233.477 ; free physical = 16988 ; free virtual = 51511 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16987 ; free virtual = 51509 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16985 ; free virtual = 51508 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16985 ; free virtual = 51508 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16985 ; free virtual = 51508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16985 ; free virtual = 51508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16985 ; free virtual = 51508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16985 ; free virtual = 51508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 3| |2 |LUT3 | 108| |3 |LUT6 | 100| |4 |RAMB36E1 | 8| |5 |FDRE | 125| |6 |IBUF | 11| |7 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 356| |2 | roi |roi | 216| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16985 ; free virtual = 51508 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 96 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 16986 ; free virtual = 51509 Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.945 ; gain = 243.492 ; free physical = 16986 ; free virtual = 51509 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 230 Infos, 96 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1472.965 ; gain = 390.074 ; free physical = 16893 ; free virtual = 51416 ROI: SLICE_X0Y0:SLICE_X43Y99 ROI: RAMB18_X0Y0:RAMB18_X2Y39 ROI: RAMB36_X0Y0:RAMB36_X2Y19 ROI: DSP48_X0Y0:DSP48_X1Y39 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1536.996 ; gain = 0.000 ; free physical = 16882 ; free virtual = 51404 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17075422c Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1536.996 ; gain = 0.000 ; free physical = 16882 ; free virtual = 51404 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1922.484 ; gain = 0.000 ; free physical = 16545 ; free virtual = 51068 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 196761f3e Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 16540 ; free virtual = 51062 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 16540 ; free virtual = 51062 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 16540 ; free virtual = 51062 Phase 1 Placer Initialization | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 16540 ; free virtual = 51062 Phase 2 Global Placement WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16523 ; free virtual = 51045 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16523 ; free virtual = 51045 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18f2ccf33 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16523 ; free virtual = 51045 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16523 ; free virtual = 51045 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16523 ; free virtual = 51045 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16520 ; free virtual = 51042 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16520 ; free virtual = 51042 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16520 ; free virtual = 51042 Phase 3 Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16520 ; free virtual = 51042 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16520 ; free virtual = 51042 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21d012c21 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16521 ; free virtual = 51044 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21d012c21 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16521 ; free virtual = 51044 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1ce33f28d Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16521 ; free virtual = 51044 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ce33f28d Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16521 ; free virtual = 51044 Ending Placer Task | Checksum: 14c774d33 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16532 ; free virtual = 51055 240 Infos, 98 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 2042.543 ; gain = 569.578 ; free physical = 16534 ; free virtual = 51057 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9c4f4a11 ConstDB: 0 ShapeSum: b0280322 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2072.188 ; gain = 29.645 ; free physical = 16330 ; free virtual = 50852 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2076.176 ; gain = 33.633 ; free physical = 16298 ; free virtual = 50821 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2076.176 ; gain = 33.633 ; free physical = 16298 ; free virtual = 50821 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b8accb7e Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16286 ; free virtual = 50809 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: fc55de3b Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16290 ; free virtual = 50813 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 0 Phase 4.1 Global Iteration 0 | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16290 ; free virtual = 50812 Phase 4 Rip-up And Reroute | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16290 ; free virtual = 50812 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16290 ; free virtual = 50812 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16290 ; free virtual = 50812 Phase 6 Post Hold Fix | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16290 ; free virtual = 50812 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0324117 % Global Horizontal Routing Utilization = 0.0410751 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. Phase 7 Route finalize | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16290 ; free virtual = 50812 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16288 ; free virtual = 50811 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16288 ; free virtual = 50811 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2092.230 ; gain = 49.688 ; free physical = 16323 ; free virtual = 50845 Routing Is Done. 247 Infos, 99 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:20 . Memory (MB): peak = 2131.020 ; gain = 88.477 ; free physical = 16323 ; free virtual = 50845 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2131.020 ; gain = 0.000 ; free physical = 16321 ; free virtual = 50846 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:04:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 257 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2472.125 ; gain = 341.105 ; free physical = 16279 ; free virtual = 50806 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:04:56 2019... mkdir -p build/basicdb cd build && python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate.py \ --tiles /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/tiles.txt \ --out /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/basicdb/tilegrid.json cd iob && make cd iob_int && make cd monitor && make cd bram && make cd bram_block && make cd bram_int && make cd clb && make cd clb_int && make cd dsp && make cd fifo_int && make cd cfg_int && make cd monitor_int && make make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 14 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dframe 26 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } # run ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # gets $fp line # # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 2] # set pin_str [lindex $line 3] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 3] # set pin_str [lindex $line 4] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30750 INFO: Launching helper process for spawning children vivado processes Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 30752 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 30771 INFO: Helper process launched with PID 30773 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30842 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30891 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30923 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30927 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30948 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31005 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31107 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31110 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 14681 ; free virtual = 49222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 14673 ; free virtual = 49214 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 14629 ; free virtual = 49170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 14615 ; free virtual = 49156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 14580 ; free virtual = 49121 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 14539 ; free virtual = 49080 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 14525 ; free virtual = 49066 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 14500 ; free virtual = 49042 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] WARNING: [Synth 8-350] instance 'dummy_lut' of module 'LUT6' requires 7 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (3#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 14387 ; free virtual = 48928 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 14457 ; free virtual = 48999 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 14455 ; free virtual = 48998 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 14435 ; free virtual = 48978 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 14435 ; free virtual = 48977 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 14434 ; free virtual = 48976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 14432 ; free virtual = 48974 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.988 ; free physical = 14438 ; free virtual = 48981 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1205.949 ; gain = 110.508 ; free physical = 14417 ; free virtual = 48959 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 14416 ; free virtual = 48958 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 14408 ; free virtual = 48951 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 14394 ; free virtual = 48936 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 14393 ; free virtual = 48936 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer --------------------------------------------------------------------------------- Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 14394 ; free virtual = 48936 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 14394 ; free virtual = 48937 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:475] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1847] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2015] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 14387 ; free virtual = 48930 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2071] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 14332 ; free virtual = 48875 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 14332 ; free virtual = 48875 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6389] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 14357 ; free virtual = 48904 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] Hierarchical RTL Component report Parameter DIN_N bound to: 8 - type: integer --------------------------------------------------------------------------------- Parameter DOUT_N bound to: 8 - type: integer Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] ---------------------------------------------------------------------------------WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 14352 ; free virtual = 48899 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 14325 ; free virtual = 48868 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 14324 ; free virtual = 48867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 14307 ; free virtual = 48850 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 14310 ; free virtual = 48853 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 14307 ; free virtual = 48850 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 14252 ; free virtual = 48795 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 14234 ; free virtual = 48777 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 14191 ; free virtual = 48738 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 14172 ; free virtual = 48724 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] Parameter SIM_DEVICE bound to: 7SERIES - type: string INFO: [Synth 8-256] done synthesizing module 'IDELAYCTRL' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] WARNING: [Synth 8-350] instance 'idelayctrl' of module 'IDELAYCTRL' requires 3 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] --------------------------------------------------------------------------------- Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter IDELAY_TYPE bound to: FIXED - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: float Parameter SIGNAL_PATTERN bound to: DATA - type: string Parameter SIM_DELAY_D bound to: 0 - type: integer Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 14163 ; free virtual = 48706 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'IDELAYE2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y11' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y12' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y15' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y16' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y17' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y18' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y21' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y22' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y23' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y24' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y25' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y26' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y27' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y28' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y29' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y30' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y3' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y4' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y33' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y34' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y35' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y36' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y39' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y40' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y41' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y42' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y45' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y46' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y47' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y48' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y5' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y6' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y9' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y10' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y100' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y149' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y50' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y99' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y107' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y108' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y119' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y120' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y131' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y132' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y143' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y144' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y57' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y58' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y69' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y70' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y81' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y82' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y93' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y94' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y113' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y114' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y137' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y138' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y63' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y64' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y87' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y88' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y101' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y102' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y103' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y104' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y105' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 14151 ; free virtual = 48695 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 14150 ; free virtual = 48694 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 14106 ; free virtual = 48654 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 14110 ; free virtual = 48655 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 14109 ; free virtual = 48654 WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.496 ; free physical = 14101 ; free virtual = 48645 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.496 ; free physical = 14099 ; free virtual = 48643 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.523 ; free physical = 14096 ; free virtual = 48641 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.523 ; free physical = 14067 ; free virtual = 48616 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 14067 ; free virtual = 48611 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 14050 ; free virtual = 48595 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 14014 ; free virtual = 48558 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 14012 ; free virtual = 48556 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 13995 ; free virtual = 48539 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 13667 ; free virtual = 48211 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 13598 ; free virtual = 48143 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 13597 ; free virtual = 48142 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1327.918 ; gain = 232.477 ; free physical = 13143 ; free virtual = 47688 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1327.918 ; gain = 232.477 ; free physical = 13107 ; free virtual = 47657 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13084 ; free virtual = 47634 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 12994 ; free virtual = 47539 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12972 ; free virtual = 47519 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 12970 ; free virtual = 47517 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12966 ; free virtual = 47511 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 12968 ; free virtual = 47513 --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12967 ; free virtual = 47512 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12963 ; free virtual = 47509 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 12959 ; free virtual = 47505 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 12954 ; free virtual = 47499 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12951 ; free virtual = 47496 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12951 ; free virtual = 47496 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 12945 ; free virtual = 47495 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 12940 ; free virtual = 47488 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 12946 ; free virtual = 47492 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 12945 ; free virtual = 47492 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 12944 ; free virtual = 47492 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 12944 ; free virtual = 47492 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 12944 ; free virtual = 47493 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12943 ; free virtual = 47493 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 12937 ; free virtual = 47490 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 12940 ; free virtual = 47490 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12942 ; free virtual = 47492 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 12904 ; free virtual = 47449 --------------------------------------------------------------------------------- No constraint files found. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.566 ; gain = 216.121 ; free physical = 12897 ; free virtual = 47442 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 12896 ; free virtual = 47441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12884 ; free virtual = 47430 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- No constraint files found. Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12883 ; free virtual = 47428 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12882 ; free virtual = 47427 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12881 ; free virtual = 47426 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 12881 ; free virtual = 47426 Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12881 ; free virtual = 47426 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12882 ; free virtual = 47427 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12882 ; free virtual = 47427 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12875 ; free virtual = 47420 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 12883 ; free virtual = 47428 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I1 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I2 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I3 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I4 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I5 to constant 0 --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12881 ; free virtual = 47426 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12877 ; free virtual = 47422 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 12871 ; free virtual = 47416 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12867 ; free virtual = 47412 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12849 ; free virtual = 47394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12865 ; free virtual = 47410 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12865 ; free virtual = 47410 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12865 ; free virtual = 47410 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT6 | 1| |2 |IBUF | 96| +------+-----+------+ --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 97| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12864 ; free virtual = 47409 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 8 warnings. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12854 ; free virtual = 47399 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12864 ; free virtual = 47409 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 12864 ; free virtual = 47409 --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-571] Translating synthesized netlist Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12845 ; free virtual = 47390 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12844 ; free virtual = 47389 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.566 ; gain = 216.121 ; free physical = 12844 ; free virtual = 47389 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12844 ; free virtual = 47389 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12843 ; free virtual = 47388 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12843 ; free virtual = 47388 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12843 ; free virtual = 47388 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12841 ; free virtual = 47386 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12841 ; free virtual = 47386 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 12842 ; free virtual = 47387 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12842 ; free virtual = 47387 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12830 ; free virtual = 47375 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12827 ; free virtual = 47373 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12825 ; free virtual = 47371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12824 ; free virtual = 47371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12824 ; free virtual = 47371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12823 ; free virtual = 47371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12823 ; free virtual = 47371 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12821 ; free virtual = 47371 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 12818 ; free virtual = 47369 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.480 ; free physical = 12807 ; free virtual = 47353 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.234 ; free physical = 12803 ; free virtual = 47348 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.234 ; free physical = 12794 ; free virtual = 47339 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.480 ; free physical = 12790 ; free virtual = 47335 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12786 ; free virtual = 47331 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12781 ; free virtual = 47326 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12784 ; free virtual = 47329 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12784 ; free virtual = 47329 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12783 ; free virtual = 47328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12783 ; free virtual = 47328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12782 ; free virtual = 47327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12782 ; free virtual = 47327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12781 ; free virtual = 47326 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12781 ; free virtual = 47326 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12782 ; free virtual = 47327 --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12782 ; free virtual = 47327 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12783 ; free virtual = 47328 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12783 ; free virtual = 47328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12782 ; free virtual = 47327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12782 ; free virtual = 47327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12782 ; free virtual = 47327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ INFO: [Project 1-571] Translating synthesized netlist Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12779 ; free virtual = 47324 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12768 ; free virtual = 47313 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 12768 ; free virtual = 47313 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12738 ; free virtual = 47283 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12736 ; free virtual = 47281 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12731 ; free virtual = 47276 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12731 ; free virtual = 47276 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12731 ; free virtual = 47276 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12730 ; free virtual = 47275 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12728 ; free virtual = 47273 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. INFO: [Project 1-570] Preparing netlist for logic optimization Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 12727 ; free virtual = 47272 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 12727 ; free virtual = 47272 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12662 ; free virtual = 47207 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12660 ; free virtual = 47205 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12658 ; free virtual = 47203 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12658 ; free virtual = 47203 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12659 ; free virtual = 47203 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12660 ; free virtual = 47205 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12662 ; free virtual = 47206 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 12660 ; free virtual = 47205 Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.914 ; gain = 218.457 ; free physical = 12661 ; free virtual = 47206 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12645 ; free virtual = 47190 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12643 ; free virtual = 47188 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12640 ; free virtual = 47185 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12639 ; free virtual = 47184 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12639 ; free virtual = 47184 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12638 ; free virtual = 47183 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |IDELAYCTRL | 1| |2 |IDELAYE2 | 200| |3 |IBUF | 200| +------+-----------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 401| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12638 ; free virtual = 47183 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 402 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 12637 ; free virtual = 47182 INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.672 ; gain = 216.211 ; free physical = 12640 ; free virtual = 47185 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 400 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 12284 ; free virtual = 46829 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1396.691 ; gain = 313.797 ; free physical = 12279 ; free virtual = 46824 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 12264 ; free virtual = 46809 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1420.934 ; gain = 338.047 ; free physical = 12269 ; free virtual = 46814 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.723 ; gain = 0.000 ; free physical = 12249 ; free virtual = 46794 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1460.723 ; gain = 0.000 ; free physical = 12249 ; free virtual = 46794 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12285 ; free virtual = 46830 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1395.719 ; gain = 312.828 ; free physical = 12313 ; free virtual = 46861 Looping LIOB33_X0Y1 0 IOB_X0Y1 {di[0]} key "IOB_X0Y1" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl" line 77) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:05:40 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1401.691 ; gain = 318.797 ; free physical = 12349 ; free virtual = 46899 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1398.688 ; gain = 315.797 ; free physical = 12421 ; free virtual = 46975 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' Makefile:57: recipe for target 'iob/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.723 ; gain = 0.000 ; free physical = 12706 ; free virtual = 47272 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1465.723 ; gain = 0.000 ; free physical = 12706 ; free virtual = 47271 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 12662 ; free virtual = 47209 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.965 ; gain = 0.000 ; free physical = 12662 ; free virtual = 47208 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1484.965 ; gain = 0.000 ; free physical = 12662 ; free virtual = 47208 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12635 ; free virtual = 47182 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12631 ; free virtual = 47178 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12596 ; free virtual = 47144 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12591 ; free virtual = 47142 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12580 ; free virtual = 47135 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12574 ; free virtual = 47131 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12570 ; free virtual = 47129 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12554 ; free virtual = 47119 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12552 ; free virtual = 47118 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 12542 ; free virtual = 47108 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 12542 ; free virtual = 47108 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 12499 ; free virtual = 47065 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 12437 ; free virtual = 46983 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 12442 ; free virtual = 46988 --------------------------------------------------------------------------------- 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 12464 ; free virtual = 47010 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y0' at site IDELAY_X0Y0, Site IOB_X0Y0 is not bonded. Place terminal di[0] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y1' at site IDELAY_X0Y1, Site IOB_X0Y1 is not bonded. Place terminal di[14] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y2' at site IDELAY_X0Y2, Site IOB_X0Y2 is not bonded. Place terminal di[15] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y29' at site IDELAY_X0Y29, Site IOB_X0Y29 is not bonded. Place terminal di[30] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y3' at site IDELAY_X0Y3, Site IOB_X0Y3 is not bonded. Place terminal di[32] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y30' at site IDELAY_X0Y30, Site IOB_X0Y30 is not bonded. Place terminal di[31] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y31' at site IDELAY_X0Y31, Site IOB_X0Y31 is not bonded. Place terminal di[4] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y32' at site IDELAY_X0Y32, Site IOB_X0Y32 is not bonded. Place terminal di[5] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y33' at site IDELAY_X0Y33, Site IOB_X0Y33 is not bonded. Place terminal di[34] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y34' at site IDELAY_X0Y34, Site IOB_X0Y34 is not bonded. Place terminal di[35] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y35' at site IDELAY_X0Y35, Site IOB_X0Y35 is not bonded. Place terminal di[36] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y36' at site IDELAY_X0Y36, Site IOB_X0Y36 is not bonded. Place terminal di[37] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y38' at site IDELAY_X0Y38, Site IOB_X0Y38 is not bonded. Place terminal di[13] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y39' at site IDELAY_X0Y39, Site IOB_X0Y39 is not bonded. Place terminal di[38] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y4' at site IDELAY_X0Y4, Site IOB_X0Y4 is not bonded. Place terminal di[33] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y40' at site IDELAY_X0Y40, Site IOB_X0Y40 is not bonded. Place terminal di[39] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y41' at site IDELAY_X0Y41, Site IOB_X0Y41 is not bonded. Place terminal di[40] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y42' at site IDELAY_X0Y42, Site IOB_X0Y42 is not bonded. Place terminal di[41] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y43' at site IDELAY_X0Y43, Site IOB_X0Y43 is not bonded. Place terminal di[6] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y44' at site IDELAY_X0Y44, Site IOB_X0Y44 is not bonded. Place terminal di[7] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y45' at site IDELAY_X0Y45, Site IOB_X0Y45 is not bonded. Place terminal di[42] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y46' at site IDELAY_X0Y46, Site IOB_X0Y46 is not bonded. Place terminal di[43] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y47' at site IDELAY_X0Y47, Site IOB_X0Y47 is not bonded. Place terminal di[44] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y48' at site IDELAY_X0Y48, Site IOB_X0Y48 is not bonded. Place terminal di[45] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y49' at site IDELAY_X0Y49, Site IOB_X0Y49 is not bonded. Place terminal di[1] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y0' at site IDELAY_X1Y0, Site IOB_X1Y0 is not bonded. Place terminal di[50] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y1' at site IDELAY_X1Y1, Site IOB_X1Y1 is not bonded. Place terminal di[92] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y10' at site IDELAY_X1Y10, Site IOB_X1Y10 is not bonded. Place terminal di[193] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2335] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y11' at site IDELAY_X1Y11, Site IOB_X1Y11 is not bonded. Place terminal di[102] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1243] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y12' at site IDELAY_X1Y12, Site IOB_X1Y12 is not bonded. Place terminal di[103] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1255] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y13' at site IDELAY_X1Y13, Site IOB_X1Y13 is not bonded. Place terminal di[82] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y14' at site IDELAY_X1Y14, Site IOB_X1Y14 is not bonded. Place terminal di[83] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y15' at site IDELAY_X1Y15, Site IOB_X1Y15 is not bonded. Place terminal di[132] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1603] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y16' at site IDELAY_X1Y16, Site IOB_X1Y16 is not bonded. Place terminal di[133] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1615] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y17' at site IDELAY_X1Y17, Site IOB_X1Y17 is not bonded. Place terminal di[134] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1627] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y18' at site IDELAY_X1Y18, Site IOB_X1Y18 is not bonded. Place terminal di[135] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1639] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y19' at site IDELAY_X1Y19, Site IOB_X1Y19 is not bonded. Place terminal di[64] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y2' at site IDELAY_X1Y2, Site IOB_X1Y2 is not bonded. Place terminal di[93] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y20' at site IDELAY_X1Y20, Site IOB_X1Y20 is not bonded. Place terminal di[65] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y21' at site IDELAY_X1Y21, Site IOB_X1Y21 is not bonded. Place terminal di[136] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1651] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y22' at site IDELAY_X1Y22, Site IOB_X1Y22 is not bonded. Place terminal di[137] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1663] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y23' at site IDELAY_X1Y23, Site IOB_X1Y23 is not bonded. Place terminal di[138] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1675] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y24' at site IDELAY_X1Y24, Site IOB_X1Y24 is not bonded. Place terminal di[139] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1687] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y25' at site IDELAY_X1Y25, Site IOB_X1Y25 is not bonded. Place terminal di[140] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1699] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y26' at site IDELAY_X1Y26, Site IOB_X1Y26 is not bonded. Place terminal di[141] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1711] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y27' at site IDELAY_X1Y27, Site IOB_X1Y27 is not bonded. Place terminal di[142] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1723] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y28' at site IDELAY_X1Y28, Site IOB_X1Y28 is not bonded. Place terminal di[143] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1735] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y29' at site IDELAY_X1Y29, Site IOB_X1Y29 is not bonded. Place terminal di[144] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1747] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y3' at site IDELAY_X1Y3, Site IOB_X1Y3 is not bonded. Place terminal di[146] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1771] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y30' at site IDELAY_X1Y30, Site IOB_X1Y30 is not bonded. Place terminal di[145] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1759] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y31' at site IDELAY_X1Y31, Site IOB_X1Y31 is not bonded. Place terminal di[66] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y32' at site IDELAY_X1Y32, Site IOB_X1Y32 is not bonded. Place terminal di[67] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y33' at site IDELAY_X1Y33, Site IOB_X1Y33 is not bonded. Place terminal di[148] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1795] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y34' at site IDELAY_X1Y34, Site IOB_X1Y34 is not bonded. Place terminal di[149] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1807] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y35' at site IDELAY_X1Y35, Site IOB_X1Y35 is not bonded. Place terminal di[150] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1819] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y36' at site IDELAY_X1Y36, Site IOB_X1Y36 is not bonded. Place terminal di[151] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1831] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y37' at site IDELAY_X1Y37, Site IOB_X1Y37 is not bonded. Place terminal di[86] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y38' at site IDELAY_X1Y38, Site IOB_X1Y38 is not bonded. Place terminal di[87] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y39' at site IDELAY_X1Y39, Site IOB_X1Y39 is not bonded. Place terminal di[152] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1843] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y4' at site IDELAY_X1Y4, Site IOB_X1Y4 is not bonded. Place terminal di[147] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1783] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y40' at site IDELAY_X1Y40, Site IOB_X1Y40 is not bonded. Place terminal di[153] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1855] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y41' at site IDELAY_X1Y41, Site IOB_X1Y41 is not bonded. Place terminal di[154] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1867] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y42' at site IDELAY_X1Y42, Site IOB_X1Y42 is not bonded. Place terminal di[155] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1879] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y43' at site IDELAY_X1Y43, Site IOB_X1Y43 is not bonded. Place terminal di[68] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y44' at site IDELAY_X1Y44, Site IOB_X1Y44 is not bonded. Place terminal di[69] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y45' at site IDELAY_X1Y45, Site IOB_X1Y45 is not bonded. Place terminal di[156] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1891] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y46' at site IDELAY_X1Y46, Site IOB_X1Y46 is not bonded. Place terminal di[157] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1903] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y47' at site IDELAY_X1Y47, Site IOB_X1Y47 is not bonded. Place terminal di[158] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1915] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y48' at site IDELAY_X1Y48, Site IOB_X1Y48 is not bonded. Place terminal di[159] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1927] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y49' at site IDELAY_X1Y49, Site IOB_X1Y49 is not bonded. Place terminal di[53] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y5' at site IDELAY_X1Y5, Site IOB_X1Y5 is not bonded. Place terminal di[160] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1939] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y6' at site IDELAY_X1Y6, Site IOB_X1Y6 is not bonded. Place terminal di[161] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1951] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y7' at site IDELAY_X1Y7, Site IOB_X1Y7 is not bonded. Place terminal di[74] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y8' at site IDELAY_X1Y8, Site IOB_X1Y8 is not bonded. Place terminal di[75] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y9' at site IDELAY_X1Y9, Site IOB_X1Y9 is not bonded. Place terminal di[192] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2323] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 18 Infos, 200 Warnings, 75 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1399.688 ; gain = 316.797 ; free physical = 12462 ; free virtual = 47008 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1404.930 ; gain = 322.039 ; free physical = 12476 ; free virtual = 47023 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Looping INT_L_X0Y0 0 IDELAY_X0Y0 IOB_X0Y0 {di[0]} key "IOB_X0Y0" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl" line 75) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:05:43 2019... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' Makefile:60: recipe for target 'iob_int/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Starting Placer Task INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 12838 ; free virtual = 47385 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1583c4629 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 12841 ; free virtual = 47387 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1416.582 ; gain = 333.695 ; free physical = 12850 ; free virtual = 47397 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Starting Placer Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 12834 ; free virtual = 47381 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 12822 ; free virtual = 47368 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 12811 ; free virtual = 47358 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 12819 ; free virtual = 47365 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.613 ; gain = 0.000 ; free physical = 12809 ; free virtual = 47356 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1482.613 ; gain = 0.000 ; free physical = 12806 ; free virtual = 47353 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 12612 ; free virtual = 47158 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 12335 ; free virtual = 46882 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 12373 ; free virtual = 46920 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 12366 ; free virtual = 46913 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1544.949 ; gain = 0.000 ; free physical = 12276 ; free virtual = 46823 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12275 ; free virtual = 46822 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.51 . Memory (MB): peak = 1544.949 ; gain = 0.000 ; free physical = 12210 ; free virtual = 46757 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12200 ; free virtual = 46747 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12184 ; free virtual = 46730 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12157 ; free virtual = 46704 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12151 ; free virtual = 46697 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12117 ; free virtual = 46664 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12104 ; free virtual = 46651 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12098 ; free virtual = 46645 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12089 ; free virtual = 46636 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 12088 ; free virtual = 46635 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.211 ; gain = 0.000 ; free physical = 11750 ; free virtual = 46297 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 11729 ; free virtual = 46276 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 11725 ; free virtual = 46272 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 11725 ; free virtual = 46272 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 11725 ; free virtual = 46271 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 11724 ; free virtual = 46271 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.254 ; gain = 443.531 ; free physical = 11725 ; free virtual = 46271 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.254 ; gain = 507.562 ; free physical = 11725 ; free virtual = 46271 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.211 ; gain = 0.000 ; free physical = 11117 ; free virtual = 45663 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 10951 ; free virtual = 45498 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 10920 ; free virtual = 45467 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 10918 ; free virtual = 45465 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 10917 ; free virtual = 45464 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 10915 ; free virtual = 45461 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 10891 ; free virtual = 45437 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.254 ; gain = 499.562 ; free physical = 10890 ; free virtual = 45437 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.453 ; gain = 0.000 ; free physical = 10769 ; free virtual = 45316 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10298 ; free virtual = 44845 Phase 1.3 Build Placer Netlist Model Starting Routing Task Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10293 ; free virtual = 44840 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10290 ; free virtual = 44837 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10289 ; free virtual = 44836 Phase 2 Global Placement INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1842.207 ; gain = 0.000 ; free physical = 10256 ; free virtual = 44803 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 10192 ; free virtual = 44739 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10b00cead Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 9862 ; free virtual = 44409 Phase 1.3 Build Placer Netlist Model INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.3 Build Placer Netlist Model | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 9841 ; free virtual = 44388 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 9822 ; free virtual = 44369 Phase 1 Placer Initialization | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 9800 ; free virtual = 44347 Phase 2 Global Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.250 ; gain = 467.531 ; free physical = 9747 ; free virtual = 44294 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.250 ; gain = 467.531 ; free physical = 9760 ; free virtual = 44307 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.250 ; gain = 467.531 ; free physical = 9758 ; free virtual = 44305 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.250 ; gain = 467.531 ; free physical = 9756 ; free virtual = 44302 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.250 ; gain = 467.531 ; free physical = 9754 ; free virtual = 44301 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.250 ; gain = 467.531 ; free physical = 9748 ; free virtual = 44294 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.250 ; gain = 531.562 ; free physical = 9747 ; free virtual = 44294 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 9697 ; free virtual = 44243 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9429 ; free virtual = 43976 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.449 ; gain = 0.000 ; free physical = 9421 ; free virtual = 43968 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32487 Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9383 ; free virtual = 43930 Phase 1.4 Constrain Clocks/Macros WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9382 ; free virtual = 43928 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9378 ; free virtual = 43925 Phase 2 Final Placement Cleanup Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 9381 ; free virtual = 43928 Phase 1.3 Build Placer Netlist Model ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9379 ; free virtual = 43926 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 9376 ; free virtual = 43923 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 9373 ; free virtual = 43920 Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9372 ; free virtual = 43919 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 9372 ; free virtual = 43918 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 9370 ; free virtual = 43917 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 9367 ; free virtual = 43913 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 9359 ; free virtual = 43906 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 581.562 ; free physical = 9357 ; free virtual = 43904 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.102 ; gain = 0.000 ; free physical = 9310 ; free virtual = 43857 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.145 ; gain = 511.531 ; free physical = 9201 ; free virtual = 43748 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.145 ; gain = 511.531 ; free physical = 9182 ; free virtual = 43729 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.145 ; gain = 511.531 ; free physical = 9185 ; free virtual = 43732 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.145 ; gain = 511.531 ; free physical = 9179 ; free virtual = 43726 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.145 ; gain = 511.531 ; free physical = 9179 ; free virtual = 43726 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.145 ; gain = 511.531 ; free physical = 9187 ; free virtual = 43733 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.145 ; gain = 577.562 ; free physical = 9187 ; free virtual = 43733 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9157 ; free virtual = 43704 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9153 ; free virtual = 43700 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9151 ; free virtual = 43698 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 3.3 Area Swap Optimization INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9124 ; free virtual = 43670 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9124 ; free virtual = 43670 Phase 3.5 Small Shape Detail Placement Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: Launching helper process for spawning children vivado processes Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: Helper process launched with PID 592 Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9056 ; free virtual = 43603 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9056 ; free virtual = 43603 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9056 ; free virtual = 43603 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9056 ; free virtual = 43603 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9055 ; free virtual = 43601 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9054 ; free virtual = 43601 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9054 ; free virtual = 43601 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9053 ; free virtual = 43600 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9053 ; free virtual = 43600 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 9066 ; free virtual = 43613 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.539 ; gain = 606.605 ; free physical = 9066 ; free virtual = 43613 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8989 ; free virtual = 43536 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8986 ; free virtual = 43532 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d4686e25 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8985 ; free virtual = 43532 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ae434bf0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8977 ; free virtual = 43524 Phase 3.4 Pipeline Register Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.4 Pipeline Register Optimization | Checksum: 177f7ac55 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8977 ; free virtual = 43523 Phase 3.5 Small Shape Detail Placement Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.5 Small Shape Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8937 ; free virtual = 43484 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8937 ; free virtual = 43483 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8935 ; free virtual = 43482 Phase 3 Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8934 ; free virtual = 43481 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8935 ; free virtual = 43482 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8933 ; free virtual = 43480 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8932 ; free virtual = 43479 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8931 ; free virtual = 43477 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8930 ; free virtual = 43477 Ending Placer Task | Checksum: 1c0d5e9dc Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8943 ; free virtual = 43490 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 659.605 ; free physical = 8943 ; free virtual = 43490 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: dc3640d2 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 8225 ; free virtual = 42772 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.438 ; gain = 0.000 ; free physical = 8122 ; free virtual = 42669 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 7995 ; free virtual = 42543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 7953 ; free virtual = 42501 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 7951 ; free virtual = 42498 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 7943 ; free virtual = 42491 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 7944 ; free virtual = 42492 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.152 ; gain = 459.203 ; free physical = 7853 ; free virtual = 42400 Phase 1.3 Build Placer Netlist Model INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 7727 ; free virtual = 42275 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 7712 ; free virtual = 42259 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 7711 ; free virtual = 42259 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 7705 ; free virtual = 42252 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.152 ; gain = 459.203 ; free physical = 7601 ; free virtual = 42149 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.152 ; gain = 459.203 ; free physical = 7586 ; free virtual = 42134 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 7622 ; free virtual = 42170 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.152 ; gain = 459.203 ; free physical = 7622 ; free virtual = 42170 Phase 2 Global Placement INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1561.863 ; gain = 0.000 ; free physical = 7534 ; free virtual = 42081 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.63 . Memory (MB): peak = 1561.863 ; gain = 0.000 ; free physical = 7527 ; free virtual = 42074 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7511 ; free virtual = 42058 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7506 ; free virtual = 42053 Phase 3.2 Commit Most Macros & LUTRAMs No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 7474 ; free virtual = 42022 --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7473 ; free virtual = 42021 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 7468 ; free virtual = 42015 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7464 ; free virtual = 42012 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7458 ; free virtual = 42006 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7451 ; free virtual = 41998 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7421 ; free virtual = 41968 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7421 ; free virtual = 41968 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7420 ; free virtual = 41968 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7419 ; free virtual = 41968 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7419 ; free virtual = 41968 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7419 ; free virtual = 41969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7419 ; free virtual = 41969 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7418 ; free virtual = 41969 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7420 ; free virtual = 41971 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 7405 ; free virtual = 41952 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 7402 ; free virtual = 41949 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7403 ; free virtual = 41950 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7400 ; free virtual = 41948 Phase 3.6 Re-assign LUT pins INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7384 ; free virtual = 41932 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7378 ; free virtual = 41925 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7371 ; free virtual = 41919 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7370 ; free virtual = 41918 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7370 ; free virtual = 41918 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7370 ; free virtual = 41918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7370 ; free virtual = 41918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7370 ; free virtual = 41918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7370 ; free virtual = 41918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7370 ; free virtual = 41918 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7370 ; free virtual = 41918 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 7371 ; free virtual = 41918 INFO: [Project 1-571] Translating synthesized netlist Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7356 ; free virtual = 41904 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7349 ; free virtual = 41896 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7346 ; free virtual = 41894 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7346 ; free virtual = 41893 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7342 ; free virtual = 41889 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 555.250 ; free physical = 7367 ; free virtual = 41915 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.199 ; gain = 632.953 ; free physical = 7367 ; free virtual = 41914 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1398.684 ; gain = 315.797 ; free physical = 7238 ; free virtual = 41786 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 7109 ; free virtual = 41657 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 7109 ; free virtual = 41657 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 1398.691 ; gain = 315.797 ; free physical = 7121 ; free virtual = 41669 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 7091 ; free virtual = 41638 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 7091 ; free virtual = 41638 Phase 1 Build RT Design | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2054.938 ; gain = 118.668 ; free physical = 6902 ; free virtual = 41449 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.926 ; gain = 124.656 ; free physical = 6866 ; free virtual = 41413 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.926 ; gain = 124.656 ; free physical = 6866 ; free virtual = 41413 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.980 ; gain = 130.711 ; free physical = 6828 ; free virtual = 41376 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.980 ; gain = 130.711 ; free physical = 6806 ; free virtual = 41353 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.980 ; gain = 130.711 ; free physical = 6802 ; free virtual = 41350 Phase 4 Rip-up And Reroute | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.980 ; gain = 130.711 ; free physical = 6802 ; free virtual = 41350 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.980 ; gain = 130.711 ; free physical = 6802 ; free virtual = 41350 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.980 ; gain = 130.711 ; free physical = 6802 ; free virtual = 41350 Phase 6 Post Hold Fix | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.980 ; gain = 130.711 ; free physical = 6802 ; free virtual = 41350 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.980 ; gain = 131.711 ; free physical = 6761 ; free virtual = 41308 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.980 ; gain = 134.711 ; free physical = 6759 ; free virtual = 41307 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.980 ; gain = 134.711 ; free physical = 6759 ; free virtual = 41307 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.980 ; gain = 134.711 ; free physical = 6790 ; free virtual = 41338 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2109.770 ; gain = 205.516 ; free physical = 6787 ; free virtual = 41335 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2109.770 ; gain = 0.000 ; free physical = 6702 ; free virtual = 41251 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 6702 ; free virtual = 41249 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2054.938 ; gain = 121.668 ; free physical = 6623 ; free virtual = 41171 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2058.926 ; gain = 125.656 ; free physical = 6579 ; free virtual = 41127 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2058.926 ; gain = 125.656 ; free physical = 6579 ; free virtual = 41127 Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.395 ; gain = 490.531 ; free physical = 6579 ; free virtual = 41127 Phase 1.3 Build Placer Netlist Model INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 6554 ; free virtual = 41102 Phase 3 Initial Routing Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.172 ; gain = 44.668 ; free physical = 6544 ; free virtual = 41092 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 6498 ; free virtual = 41046 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 6497 ; free virtual = 41045 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 6480 ; free virtual = 41028 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18e90f676 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 6465 ; free virtual = 41013 Phase 4 Rip-up And Reroute | Checksum: 18e90f676 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 6465 ; free virtual = 41013 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18e90f676 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 6465 ; free virtual = 41012 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18e90f676 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 6465 ; free virtual = 41012 Phase 6 Post Hold Fix | Checksum: 18e90f676 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 6464 ; free virtual = 41012 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Loading data files... Phase 7 Route finalize | Checksum: 18e90f676 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 6483 ; free virtual = 41030 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18e90f676 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2067.980 ; gain = 134.711 ; free physical = 6481 ; free virtual = 41029 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18e90f676 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2067.980 ; gain = 134.711 ; free physical = 6481 ; free virtual = 41029 Phase 1 Build RT Design | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2056.934 ; gain = 94.668 ; free physical = 6512 ; free virtual = 41060 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2067.980 ; gain = 134.711 ; free physical = 6514 ; free virtual = 41062 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2106.770 ; gain = 205.516 ; free physical = 6512 ; free virtual = 41060 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.922 ; gain = 99.656 ; free physical = 6477 ; free virtual = 41024 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.922 ; gain = 99.656 ; free physical = 6477 ; free virtual = 41024 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 6474 ; free virtual = 41022 Phase 3 Initial Routing Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2106.770 ; gain = 0.000 ; free physical = 6474 ; free virtual = 41023 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 105.711 ; free physical = 6471 ; free virtual = 41019 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 6465 ; free virtual = 41013 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 6461 ; free virtual = 41009 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 6460 ; free virtual = 41008 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 6459 ; free virtual = 41007 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 6454 ; free virtual = 41002 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 6453 ; free virtual = 41001 Phase 7 Route finalize Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2062.176 ; gain = 43.668 ; free physical = 6443 ; free virtual = 40991 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.164 ; gain = 49.656 ; free physical = 6398 ; free virtual = 40946 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.164 ; gain = 49.656 ; free physical = 6398 ; free virtual = 40946 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 6389 ; free virtual = 40937 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 6379 ; free virtual = 40927 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 6371 ; free virtual = 40919 Phase 9 Depositing Routes Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 6367 ; free virtual = 40915 Phase 4 Rip-up And Reroute | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 6365 ; free virtual = 40913 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 6364 ; free virtual = 40912 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 6363 ; free virtual = 40911 Phase 6 Post Hold Fix | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 6362 ; free virtual = 40910 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 6350 ; free virtual = 40898 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 6389 ; free virtual = 40937 Routing Is Done. Phase 7 Route finalize | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 6389 ; free virtual = 40937 Phase 8 Verifying routed nets 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2128.254 ; gain = 136.766 ; free physical = 6386 ; free virtual = 40934 Verification completed successfully Phase 8 Verifying routed nets | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 109.711 ; free physical = 6388 ; free virtual = 40936 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 109.711 ; free physical = 6389 ; free virtual = 40937 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 109.711 ; free physical = 6420 ; free virtual = 40968 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2110.766 ; gain = 180.516 ; free physical = 6419 ; free virtual = 40967 Phase 1 Build RT Design | Checksum: edf89240 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.828 ; gain = 41.668 ; free physical = 6437 ; free virtual = 40985 Writing placer database... Number of Nodes with overlaps = 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2077.219 ; gain = 58.711 ; free physical = 6436 ; free virtual = 40984 Phase 3 Initial Routing Writing placer database... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: edf89240 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.816 ; gain = 48.656 ; free physical = 6402 ; free virtual = 40951 Phase 2.2 Pre Route Cleanup Writing XDEF routing. Phase 2.2 Pre Route Cleanup | Checksum: edf89240 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.816 ; gain = 48.656 ; free physical = 6400 ; free virtual = 40948 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 6391 ; free virtual = 40942 Writing XDEF routing. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Write XDEF Complete: Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.40 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 6383 ; free virtual = 40935 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 6352 ; free virtual = 40903 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 6332 ; free virtual = 40884 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 6329 ; free virtual = 40881 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 6327 ; free virtual = 40879 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 6322 ; free virtual = 40874 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 6318 ; free virtual = 40870 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 6322 ; free virtual = 40871 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.219 ; gain = 63.711 ; free physical = 6319 ; free virtual = 40868 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.219 ; gain = 63.711 ; free physical = 6300 ; free virtual = 40849 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.219 ; gain = 63.711 ; free physical = 6332 ; free virtual = 40881 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2121.008 ; gain = 134.516 ; free physical = 6329 ; free virtual = 40878 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1446d92b6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.121 ; gain = 60.961 ; free physical = 6311 ; free virtual = 40860 Phase 3 Initial Routing Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2121.008 ; gain = 0.000 ; free physical = 6236 ; free virtual = 40787 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.121 ; gain = 61.961 ; free physical = 6248 ; free virtual = 40798 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.121 ; gain = 61.961 ; free physical = 6246 ; free virtual = 40795 Phase 4 Rip-up And Reroute | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.121 ; gain = 61.961 ; free physical = 6243 ; free virtual = 40793 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.121 ; gain = 61.961 ; free physical = 6241 ; free virtual = 40791 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.121 ; gain = 61.961 ; free physical = 6238 ; free virtual = 40787 Phase 6 Post Hold Fix | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.121 ; gain = 61.961 ; free physical = 6235 ; free virtual = 40785 Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2071.184 ; gain = 43.645 ; free physical = 6235 ; free virtual = 40784 Phase 7 Route finalize Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2076.172 ; gain = 48.633 ; free physical = 6195 ; free virtual = 40744 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2076.172 ; gain = 48.633 ; free physical = 6196 ; free virtual = 40745 Running DRC as a precondition to command write_bitstream Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.121 ; gain = 62.961 ; free physical = 6216 ; free virtual = 40766 Phase 8 Verifying routed nets Verification completed successfully Command: report_drc (run_mandatory_drcs) for: bitstream_checks Phase 8 Verifying routed nets | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.121 ; gain = 64.961 ; free physical = 6212 ; free virtual = 40761 Phase 9 Depositing Routes INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.121 ; gain = 64.961 ; free physical = 6153 ; free virtual = 40702 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.121 ; gain = 64.961 ; free physical = 6181 ; free virtual = 40730 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2129.910 ; gain = 135.766 ; free physical = 6179 ; free virtual = 40728 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2129.910 ; gain = 0.000 ; free physical = 5968 ; free virtual = 40520 Number of Nodes with overlaps = 0 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5979 ; free virtual = 40532 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.203 ; gain = 0.000 ; free physical = 5918 ; free virtual = 40471 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5932 ; free virtual = 40482 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5939 ; free virtual = 40489 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5939 ; free virtual = 40488 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5939 ; free virtual = 40488 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5939 ; free virtual = 40488 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5939 ; free virtual = 40488 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1 Build RT Design | Checksum: 14af9d38a Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 5938 ; free virtual = 40488 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5920 ; free virtual = 40470 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5921 ; free virtual = 40471 Phase 9 Depositing Routes Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5917 ; free virtual = 40467 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 490.531 ; free physical = 5928 ; free virtual = 40477 Phase 1.4 Constrain Clocks/Macros INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2095.227 ; gain = 67.688 ; free physical = 5946 ; free virtual = 40496 Routing Is Done. 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2134.016 ; gain = 106.477 ; free physical = 5943 ; free virtual = 40493 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14af9d38a Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 5902 ; free virtual = 40452 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14af9d38a Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 5899 ; free virtual = 40449 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2134.016 ; gain = 0.000 ; free physical = 5858 ; free virtual = 40409 Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 490.531 ; free physical = 5868 ; free virtual = 40419 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 490.531 ; free physical = 5839 ; free virtual = 40389 Phase 2 Final Placement Cleanup WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 490.531 ; free physical = 5790 ; free virtual = 40341 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 490.531 ; free physical = 5583 ; free virtual = 40133 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 5554 ; free virtual = 40104 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b9dafcfc Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5520 ; free virtual = 40070 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 5569 ; free virtual = 40120 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 5584 ; free virtual = 40134 Phase 1.4 Constrain Clocks/Macros INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 5588 ; free virtual = 40138 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 5602 ; free virtual = 40152 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 5607 ; free virtual = 40157 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 5613 ; free virtual = 40163 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1931.246 ; gain = 532.562 ; free physical = 5614 ; free virtual = 40164 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1843.211 ; gain = 0.000 ; free physical = 5615 ; free virtual = 40165 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5590 ; free virtual = 40140 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5574 ; free virtual = 40124 Phase 4 Rip-up And Reroute | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5574 ; free virtual = 40124 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5571 ; free virtual = 40121 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5569 ; free virtual = 40119 Phase 6 Post Hold Fix | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5562 ; free virtual = 40112 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 12510dc3b Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5507 ; free virtual = 40057 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12510dc3b Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5502 ; free virtual = 40052 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12510dc3b Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5478 ; free virtual = 40029 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 17.688 ; free physical = 5514 ; free virtual = 40064 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2141.016 ; gain = 56.477 ; free physical = 5510 ; free virtual = 40060 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2141.016 ; gain = 0.000 ; free physical = 5494 ; free virtual = 40046 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.254 ; gain = 468.531 ; free physical = 5477 ; free virtual = 40029 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.254 ; gain = 468.531 ; free physical = 5461 ; free virtual = 40014 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.254 ; gain = 468.531 ; free physical = 5457 ; free virtual = 40010 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.254 ; gain = 468.531 ; free physical = 5458 ; free virtual = 40010 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.254 ; gain = 468.531 ; free physical = 5458 ; free virtual = 40011 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.254 ; gain = 468.531 ; free physical = 5458 ; free virtual = 40010 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.254 ; gain = 532.562 ; free physical = 5458 ; free virtual = 40010 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading data files... Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Loading data files... Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Loading route data... Processing options... Creating bitmap... Loading data files... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Loading site data... Loading route data... Creating bitstream... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 2451.875 ; gain = 342.105 ; free physical = 3200 ; free virtual = 37755 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:15 2019... Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading route data... Processing options... Creating bitmap... touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 Creating bitstream... Creating bitstream... Creating bitstream... Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... Writing bitstream ./design.bit... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2451.875 ; gain = 345.105 ; free physical = 5247 ; free virtual = 39818 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:24 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2130.957 ; gain = 30.758 ; free physical = 6211 ; free virtual = 40782 touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2135.945 ; gain = 35.746 ; free physical = 6178 ; free virtual = 40749 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2135.945 ; gain = 35.746 ; free physical = 6178 ; free virtual = 40749 Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6110 ; free virtual = 40681 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6252 ; free virtual = 40827 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6261 ; free virtual = 40836 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6261 ; free virtual = 40836 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6262 ; free virtual = 40836 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6262 ; free virtual = 40837 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6262 ; free virtual = 40837 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:25 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6335 ; free virtual = 40909 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6341 ; free virtual = 40916 Phase 9 Depositing Routes 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2462.930 ; gain = 334.676 ; free physical = 6345 ; free virtual = 40920 Creating bitstream... INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:25 2019... Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6396 ; free virtual = 40971 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2155.000 ; gain = 54.801 ; free physical = 6476 ; free virtual = 41051 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:53 . Memory (MB): peak = 2193.789 ; gain = 93.590 ; free physical = 6482 ; free virtual = 41057 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:25 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 6538 ; free virtual = 41113 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:25 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing placer database... Bitstream size: 4243411 bytes Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Writing bitstream ./design.bit... touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:26 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 2465.121 ; gain = 331.105 ; free physical = 8487 ; free virtual = 43071 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:26 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_002 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 2460.113 ; gain = 339.105 ; free physical = 10128 ; free virtual = 44732 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:28 2019... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.789 ; gain = 0.000 ; free physical = 10140 ; free virtual = 44746 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:29 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.016 ; gain = 340.105 ; free physical = 11049 ; free virtual = 45634 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:29 2019... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:31 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2475.121 ; gain = 334.105 ; free physical = 12046 ; free virtual = 46633 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:31 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2643 Phase 1 Build RT Design | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2055.938 ; gain = 92.668 ; free physical = 12086 ; free virtual = 46674 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2060.926 ; gain = 97.656 ; free physical = 12042 ; free virtual = 46630 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2060.926 ; gain = 97.656 ; free physical = 12041 ; free virtual = 46629 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 927a5c4b Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.980 ; gain = 104.711 ; free physical = 11915 ; free virtual = 46503 Phase 3 Initial Routing ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 11959 ; free virtual = 46546 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 11996 ; free virtual = 46583 Phase 4 Rip-up And Reroute | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 11995 ; free virtual = 46583 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 11995 ; free virtual = 46583 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 11995 ; free virtual = 46582 Phase 6 Post Hold Fix | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 11995 ; free virtual = 46582 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 11970 ; free virtual = 46558 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.980 ; gain = 108.711 ; free physical = 11968 ; free virtual = 46556 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.980 ; gain = 108.711 ; free physical = 11967 ; free virtual = 46554 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.980 ; gain = 108.711 ; free physical = 11997 ; free virtual = 46585 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2110.770 ; gain = 179.516 ; free physical = 11996 ; free virtual = 46584 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 11973 ; free virtual = 46563 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2697 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2748 Phase 1 Build RT Design | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2054.930 ; gain = 91.668 ; free physical = 11733 ; free virtual = 46321 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2059.918 ; gain = 96.656 ; free physical = 11695 ; free virtual = 46284 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2059.918 ; gain = 96.656 ; free physical = 11694 ; free virtual = 46282 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2776 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: e91ff6d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2134.078 ; gain = 49.668 ; free physical = 11690 ; free virtual = 46278 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.973 ; gain = 103.711 ; free physical = 11647 ; free virtual = 46236 Phase 3 Initial Routing Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: Launching helper process for spawning children vivado processes Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 103.711 ; free physical = 11527 ; free virtual = 46115 INFO: Helper process launched with PID 2831 Phase 2.1 Fix Topology Constraints Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 103.711 ; free physical = 11588 ; free virtual = 46176 Phase 4 Rip-up And Reroute | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 103.711 ; free physical = 11588 ; free virtual = 46176 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 103.711 ; free physical = 11588 ; free virtual = 46176 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 103.711 ; free physical = 11588 ; free virtual = 46176 Phase 6 Post Hold Fix | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 103.711 ; free physical = 11588 ; free virtual = 46176 Phase 2.1 Fix Topology Constraints | Checksum: e91ff6d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 11580 ; free virtual = 46168 Phase 2.2 Pre Route Cleanup Phase 7 Route finalize Phase 2.2 Pre Route Cleanup | Checksum: e91ff6d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 11578 ; free virtual = 46167 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 11547 ; free virtual = 46135 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.973 ; gain = 107.711 ; free physical = 11542 ; free virtual = 46130 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.973 ; gain = 107.711 ; free physical = 11538 ; free virtual = 46126 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.973 ; gain = 107.711 ; free physical = 11565 ; free virtual = 46153 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2109.762 ; gain = 178.516 ; free physical = 11564 ; free virtual = 46152 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 11461 ; free virtual = 46051 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11454 ; free virtual = 46042 Phase 3 Initial Routing Creating bitstream... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11446 ; free virtual = 46034 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11436 ; free virtual = 46024 Phase 4 Rip-up And Reroute | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11431 ; free virtual = 46019 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11424 ; free virtual = 46013 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11424 ; free virtual = 46012 Phase 6 Post Hold Fix | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11426 ; free virtual = 46015 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11481 ; free virtual = 46069 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11477 ; free virtual = 46066 Phase 9 Depositing Routes INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11475 ; free virtual = 46063 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11423 ; free virtual = 46011 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.496 ; gain = 95.086 ; free physical = 11461 ; free virtual = 46050 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2218.285 ; gain = 165.891 ; free physical = 11459 ; free virtual = 46048 Writing placer database... Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2893 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 11360 ; free virtual = 45964 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 11398 ; free virtual = 46003 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 11396 ; free virtual = 46002 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 11420 ; free virtual = 46025 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2929 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.285 ; gain = 0.000 ; free physical = 11294 ; free virtual = 45915 Loading data files... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2990 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10942 ; free virtual = 45538 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:07:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 2533.895 ; gain = 340.105 ; free physical = 10947 ; free virtual = 45543 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:07:55 2019... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10945 ; free virtual = 45541 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10916 ; free virtual = 45512 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 DONE Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11881 ; free virtual = 46476 --------------------------------------------------------------------------------- touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11762 ; free virtual = 46359 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11805 ; free virtual = 46401 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11805 ; free virtual = 46402 --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11826 ; free virtual = 46424 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11830 ; free virtual = 46427 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000001 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string Report RTL Partitions: INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11862 ; free virtual = 46460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11865 ; free virtual = 46463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11890 ; free virtual = 46488 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11898 ; free virtual = 46497 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 11896 ; free virtual = 46495 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 11848 ; free virtual = 46447 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 11844 ; free virtual = 46443 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11842 ; free virtual = 46441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11838 ; free virtual = 46437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1205.949 ; gain = 110.508 ; free physical = 11823 ; free virtual = 46420 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11804 ; free virtual = 46402 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11597 ; free virtual = 46194 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11552 ; free virtual = 46150 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11545 ; free virtual = 46142 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 11451 ; free virtual = 46048 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11399 ; free virtual = 45997 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11399 ; free virtual = 45996 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11397 ; free virtual = 45994 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11396 ; free virtual = 45994 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11396 ; free virtual = 45994 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11392 ; free virtual = 45989 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11391 ; free virtual = 45989 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11386 ; free virtual = 45984 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 11386 ; free virtual = 45984 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 11344 ; free virtual = 45942 --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 11258 ; free virtual = 45856 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 11196 ; free virtual = 45794 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 11195 ; free virtual = 45793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 11187 ; free virtual = 45785 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading site data... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 11020 ; free virtual = 45619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 10974 ; free virtual = 45572 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 10938 ; free virtual = 45537 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 10936 ; free virtual = 45536 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 11100 ; free virtual = 45702 --------------------------------------------------------------------------------- Creating bitstream... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1396.684 ; gain = 313.797 ; free physical = 10998 ; free virtual = 45601 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 11032 ; free virtual = 45635 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 11031 ; free virtual = 45635 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11018 ; free virtual = 45625 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 11013 ; free virtual = 45616 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11009 ; free virtual = 45616 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11002 ; free virtual = 45610 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 10984 ; free virtual = 45587 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 10983 ; free virtual = 45586 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.930 ; gain = 211.484 ; free physical = 10983 ; free virtual = 45586 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1327.918 ; gain = 232.477 ; free physical = 10970 ; free virtual = 45573 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.961 ; gain = 115.508 ; free physical = 10969 ; free virtual = 45573 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: No constraint files found. +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1327.918 ; gain = 232.477 ; free physical = 10960 ; free virtual = 45563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.930 ; gain = 211.484 ; free physical = 10960 ; free virtual = 45563 | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10960 ; free virtual = 45563 +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10951 ; free virtual = 45554 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10942 ; free virtual = 45545 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10939 ; free virtual = 45543 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10935 ; free virtual = 45539 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10888 ; free virtual = 45491 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10887 ; free virtual = 45490 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10885 ; free virtual = 45488 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10885 ; free virtual = 45488 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10886 ; free virtual = 45489 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10886 ; free virtual = 45489 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10885 ; free virtual = 45488 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10880 ; free virtual = 45483 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 10882 ; free virtual = 45485 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10826 ; free virtual = 45430 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10826 ; free virtual = 45430 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10826 ; free virtual = 45430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10826 ; free virtual = 45430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10825 ; free virtual = 45430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10825 ; free virtual = 45430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10824 ; free virtual = 45429 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 10823 ; free virtual = 45429 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 10822 ; free virtual = 45428 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10809 ; free virtual = 45416 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10811 ; free virtual = 45418 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10814 ; free virtual = 45421 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10838 ; free virtual = 45445 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10840 ; free virtual = 45447 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10838 ; free virtual = 45445 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10848 ; free virtual = 45455 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10849 ; free virtual = 45456 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10846 ; free virtual = 45453 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10842 ; free virtual = 45448 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10859 ; free virtual = 45466 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10854 ; free virtual = 45461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10849 ; free virtual = 45456 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10864 ; free virtual = 45471 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10847 ; free virtual = 45454 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 10846 ; free virtual = 45453 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.914 ; gain = 219.461 ; free physical = 10851 ; free virtual = 45458 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 10850 ; free virtual = 45457 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:08:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2454.875 ; gain = 344.105 ; free physical = 10968 ; free virtual = 45576 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:08:07 2019... INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Project 1-570] Preparing netlist for logic optimization touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 11587 ; free virtual = 46194 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 11528 ; free virtual = 46135 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11588 ; free virtual = 46195 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 11482 ; free virtual = 46089 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:08:10 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2452.867 ; gain = 343.105 ; free physical = 11406 ; free virtual = 46017 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:08:10 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11495 ; free virtual = 46102 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11497 ; free virtual = 46104 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11538 ; free virtual = 46145 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11605 ; free virtual = 46212 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.570 ; gain = 218.121 ; free physical = 11619 ; free virtual = 46226 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11693 ; free virtual = 46300 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11744 ; free virtual = 46351 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11838 ; free virtual = 46445 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 12089 ; free virtual = 46697 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 12143 ; free virtual = 46750 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully INFO: [Project 1-571] Translating synthesized netlist synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1420.934 ; gain = 338.047 ; free physical = 12345 ; free virtual = 46953 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Bitstream size: 4243411 bytes INFO: [DRC 23-27] Running DRC with 8 threads Config size: 1060815 words Number of configuration frames: 9996 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design DONE Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Starting Placer Task No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.570 ; gain = 218.121 ; free physical = 12347 ; free virtual = 46953 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1401.688 ; gain = 318.797 ; free physical = 12346 ; free virtual = 46953 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 12339 ; free virtual = 46946 Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 12339 ; free virtual = 46946 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12328 ; free virtual = 46935 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 12267 ; free virtual = 46874 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 12267 ; free virtual = 46874 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.922 ; gain = 324.031 ; free physical = 12323 ; free virtual = 46930 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.965 ; gain = 0.000 ; free physical = 12311 ; free virtual = 46918 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1484.965 ; gain = 0.000 ; free physical = 12311 ; free virtual = 46918 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 12335 ; free virtual = 46942 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12333 ; free virtual = 46940 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12332 ; free virtual = 46939 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12331 ; free virtual = 46938 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12331 ; free virtual = 46938 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12331 ; free virtual = 46938 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12331 ; free virtual = 46938 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12330 ; free virtual = 46937 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.547 ; gain = 226.098 ; free physical = 12328 ; free virtual = 46935 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1321.555 ; gain = 226.098 ; free physical = 12330 ; free virtual = 46937 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 12329 ; free virtual = 46936 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12323 ; free virtual = 46930 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 12284 ; free virtual = 46891 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 12281 ; free virtual = 46888 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12283 ; free virtual = 46890 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12280 ; free virtual = 46887 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12275 ; free virtual = 46882 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12273 ; free virtual = 46880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12272 ; free virtual = 46879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12260 ; free virtual = 46867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12259 ; free virtual = 46866 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 12254 ; free virtual = 46861 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.949 ; gain = 246.488 ; free physical = 12255 ; free virtual = 46862 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Loading site data... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading route data... INFO: [Project 1-570] Preparing netlist for logic optimization Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-570] Preparing netlist for logic optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 11957 ; free virtual = 46564 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3404 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1469.707 ; gain = 0.000 ; free physical = 11844 ; free virtual = 46451 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1469.707 ; gain = 0.000 ; free physical = 11839 ; free virtual = 46446 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1416.578 ; gain = 333.688 ; free physical = 11721 ; free virtual = 46329 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.941 ; gain = 342.047 ; free physical = 11611 ; free virtual = 46218 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Placer Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.609 ; gain = 0.000 ; free physical = 11555 ; free virtual = 46162 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1483.609 ; gain = 0.000 ; free physical = 11519 ; free virtual = 46127 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 11325 ; free virtual = 45932 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d7f8aeb2 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 11306 ; free virtual = 45913 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.203 ; gain = 0.000 ; free physical = 11229 ; free virtual = 45836 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11225 ; free virtual = 45832 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11223 ; free virtual = 45830 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11223 ; free virtual = 45830 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11223 ; free virtual = 45830 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11223 ; free virtual = 45830 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11223 ; free virtual = 45831 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.246 ; gain = 507.562 ; free physical = 11223 ; free virtual = 45831 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 10939 ; free virtual = 45546 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.207 ; gain = 0.000 ; free physical = 10940 ; free virtual = 45551 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10925 ; free virtual = 45536 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10916 ; free virtual = 45527 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10915 ; free virtual = 45526 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10922 ; free virtual = 45534 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10922 ; free virtual = 45534 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10923 ; free virtual = 45534 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 499.562 ; free physical = 10923 ; free virtual = 45534 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3562 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 10199 ; free virtual = 44811 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.453 ; gain = 0.000 ; free physical = 9843 ; free virtual = 44454 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:08:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:40 . Memory (MB): peak = 2605.906 ; gain = 387.621 ; free physical = 9811 ; free virtual = 44422 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:08:34 2019... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 9857 ; free virtual = 44467 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 9878 ; free virtual = 44487 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 9887 ; free virtual = 44497 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 9891 ; free virtual = 44501 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 9891 ; free virtual = 44501 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 9901 ; free virtual = 44510 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 9901 ; free virtual = 44511 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:16] WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10877 ; free virtual = 45487 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10876 ; free virtual = 45486 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10876 ; free virtual = 45486 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10876 ; free virtual = 45486 Phase 2 Global Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.441 ; gain = 0.000 ; free physical = 10847 ; free virtual = 45457 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device touch build/specimen_001/OK WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:7] GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 10845 ; free virtual = 45457 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 10853 ; free virtual = 45468 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 10844 ; free virtual = 45460 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 10831 ; free virtual = 45448 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 10825 ; free virtual = 45443 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10827 ; free virtual = 45439 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Routing Task Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 10819 ; free virtual = 45431 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.484 ; gain = 584.562 ; free physical = 10818 ; free virtual = 45430 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10710 ; free virtual = 45322 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 10707 ; free virtual = 45319 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4130 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10390 ; free virtual = 45008 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10385 ; free virtual = 45002 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10368 ; free virtual = 44985 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10335 ; free virtual = 44952 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10334 ; free virtual = 44951 Phase 3.5 Small Shape Detail Placement INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10258 ; free virtual = 44875 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10258 ; free virtual = 44875 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10258 ; free virtual = 44875 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10258 ; free virtual = 44875 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10256 ; free virtual = 44874 Phase 4.2 Post Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.195 ; gain = 0.000 ; free physical = 10255 ; free virtual = 44873 Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10255 ; free virtual = 44873 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10257 ; free virtual = 44874 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10257 ; free virtual = 44874 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10256 ; free virtual = 44874 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2043.547 ; gain = 558.582 ; free physical = 10266 ; free virtual = 44883 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2043.547 ; gain = 622.613 ; free physical = 10266 ; free virtual = 44883 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 516.531 ; free physical = 10203 ; free virtual = 44820 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 516.531 ; free physical = 10192 ; free virtual = 44809 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 516.531 ; free physical = 10178 ; free virtual = 44795 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 516.531 ; free physical = 10172 ; free virtual = 44789 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 516.531 ; free physical = 10169 ; free virtual = 44786 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 516.531 ; free physical = 10167 ; free virtual = 44785 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.238 ; gain = 580.562 ; free physical = 10167 ; free virtual = 44784 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 10163 ; free virtual = 44780 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 9975 ; free virtual = 44593 --------------------------------------------------------------------------------- Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.098 ; gain = 0.000 ; free physical = 9623 ; free virtual = 44240 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.141 ; gain = 510.531 ; free physical = 9483 ; free virtual = 44100 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.141 ; gain = 510.531 ; free physical = 9452 ; free virtual = 44069 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.141 ; gain = 510.531 ; free physical = 9435 ; free virtual = 44053 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.141 ; gain = 510.531 ; free physical = 9417 ; free virtual = 44034 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.141 ; gain = 510.531 ; free physical = 9400 ; free virtual = 44017 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] Ending Placer Task | Checksum: a55af8d3 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.141 ; gain = 510.531 ; free physical = 9380 ; free virtual = 43998 WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.141 ; gain = 577.562 ; free physical = 9378 ; free virtual = 43995 WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9374 ; free virtual = 43992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9350 ; free virtual = 43967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9360 ; free virtual = 43978 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9335 ; free virtual = 43952 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.461 ; gain = 0.000 ; free physical = 9332 ; free virtual = 43949 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ddcd7ec8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 9239 ; free virtual = 43856 Phase 1.3 Build Placer Netlist Model No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 9232 ; free virtual = 43850 Phase 1.4 Constrain Clocks/Macros report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.4 Constrain Clocks/Macros | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 9232 ; free virtual = 43850 Starting Routing Task Phase 1 Placer Initialization | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 9231 ; free virtual = 43849 Phase 2 Global Placement INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9190 ; free virtual = 43807 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9147 ; free virtual = 43765 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 9068 ; free virtual = 43686 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9064 ; free virtual = 43682 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8945 ; free virtual = 43563 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8942 ; free virtual = 43560 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8934 ; free virtual = 43552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8934 ; free virtual = 43552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8932 ; free virtual = 43550 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8932 ; free virtual = 43550 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8931 ; free virtual = 43549 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8929 ; free virtual = 43547 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 8931 ; free virtual = 43549 INFO: [Project 1-571] Translating synthesized netlist Phase 2 Global Placement | Checksum: 26d08ed71 Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8912 ; free virtual = 43530 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26d08ed71 Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8890 ; free virtual = 43507 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 20d0b931e WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8885 ; free virtual = 43502 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1e6e670e9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8920 ; free virtual = 43537 Phase 3.4 Pipeline Register Optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 8920 ; free virtual = 43538 --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 1b09ad14e Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8919 ; free virtual = 43537 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 8906 ; free virtual = 43524 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 8904 ; free virtual = 43522 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 8899 ; free virtual = 43517 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 3.5 Small Shape Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8803 ; free virtual = 43421 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8798 ; free virtual = 43416 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8794 ; free virtual = 43412 Phase 3 Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8793 ; free virtual = 43410 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8788 ; free virtual = 43406 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8822 ; free virtual = 43440 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8821 ; free virtual = 43439 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8818 ; free virtual = 43436 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8817 ; free virtual = 43434 Ending Placer Task | Checksum: 1c94b2d26 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 8823 ; free virtual = 43440 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.547 ; gain = 659.605 ; free physical = 8815 ; free virtual = 43433 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4ab841c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 8523 ; free virtual = 43141 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 8505 ; free virtual = 43123 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8497 ; free virtual = 43115 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8374 ; free virtual = 42992 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8374 ; free virtual = 42992 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8372 ; free virtual = 42989 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8372 ; free virtual = 42989 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8371 ; free virtual = 42989 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8371 ; free virtual = 42988 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8369 ; free virtual = 42987 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8368 ; free virtual = 42986 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 8370 ; free virtual = 42987 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 8244 ; free virtual = 42862 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 8227 ; free virtual = 42845 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8218 ; free virtual = 42836 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 8108 ; free virtual = 42726 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8104 ; free virtual = 42722 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8103 ; free virtual = 42721 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8103 ; free virtual = 42721 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8103 ; free virtual = 42721 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8098 ; free virtual = 42716 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8097 ; free virtual = 42715 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8097 ; free virtual = 42715 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8096 ; free virtual = 42713 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8096 ; free virtual = 42714 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 8091 ; free virtual = 42709 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 8001 ; free virtual = 42619 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 8001 ; free virtual = 42619 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5362 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 8003 ; free virtual = 42621 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 8014 ; free virtual = 42632 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1401.684 ; gain = 318.797 ; free physical = 7933 ; free virtual = 42551 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.715 ; gain = 0.000 ; free physical = 7887 ; free virtual = 42505 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1465.715 ; gain = 0.000 ; free physical = 7886 ; free virtual = 42504 Phase 1 Build RT Design | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2055.930 ; gain = 119.668 ; free physical = 7810 ; free virtual = 42428 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 7775 ; free virtual = 42393 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 7775 ; free virtual = 42393 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7771 ; free virtual = 42389 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7754 ; free virtual = 42372 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7751 ; free virtual = 42369 Phase 4 Rip-up And Reroute | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7751 ; free virtual = 42369 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7751 ; free virtual = 42369 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7751 ; free virtual = 42369 Phase 6 Post Hold Fix | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7751 ; free virtual = 42369 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7740 ; free virtual = 42358 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 7738 ; free virtual = 42356 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 7738 ; free virtual = 42356 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 7771 ; free virtual = 42389 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2108.762 ; gain = 204.516 ; free physical = 7771 ; free virtual = 42389 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2108.762 ; gain = 0.000 ; free physical = 7755 ; free virtual = 42375 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 7711 ; free virtual = 42330 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2053.934 ; gain = 120.668 ; free physical = 7539 ; free virtual = 42158 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2058.922 ; gain = 125.656 ; free physical = 7488 ; free virtual = 42106 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2058.922 ; gain = 125.656 ; free physical = 7488 ; free virtual = 42106 Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 7500 ; free virtual = 42118 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 7492 ; free virtual = 42110 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 7492 ; free virtual = 42110 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 7491 ; free virtual = 42110 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 7491 ; free virtual = 42110 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 7491 ; free virtual = 42110 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 7491 ; free virtual = 42110 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 7485 ; free virtual = 42104 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 7484 ; free virtual = 42103 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 7484 ; free virtual = 42102 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 7517 ; free virtual = 42135 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2107.766 ; gain = 206.516 ; free physical = 7516 ; free virtual = 42135 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2107.766 ; gain = 0.000 ; free physical = 7508 ; free virtual = 42127 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 1016daa37 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 7325 ; free virtual = 41943 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1016daa37 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 7275 ; free virtual = 41894 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1016daa37 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 7275 ; free virtual = 41894 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7195 ; free virtual = 41814 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7211 ; free virtual = 41829 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7202 ; free virtual = 41821 Phase 4 Rip-up And Reroute | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7202 ; free virtual = 41820 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7202 ; free virtual = 41820 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7201 ; free virtual = 41820 Phase 6 Post Hold Fix | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7201 ; free virtual = 41820 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7141 ; free virtual = 41760 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 7140 ; free virtual = 41758 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 7129 ; free virtual = 41747 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 7159 ; free virtual = 41778 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2111.766 ; gain = 179.516 ; free physical = 7150 ; free virtual = 41768 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2111.766 ; gain = 0.000 ; free physical = 7010 ; free virtual = 41629 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 6807 ; free virtual = 41426 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.168 ; gain = 44.668 ; free physical = 6846 ; free virtual = 41464 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.156 ; gain = 49.656 ; free physical = 6763 ; free virtual = 41381 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.156 ; gain = 49.656 ; free physical = 6769 ; free virtual = 41388 Loading data files... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2062.922 ; gain = 44.668 ; free physical = 6702 ; free virtual = 41322 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.910 ; gain = 49.656 ; free physical = 6632 ; free virtual = 41251 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.910 ; gain = 49.656 ; free physical = 6626 ; free virtual = 41245 Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2070.184 ; gain = 26.637 ; free physical = 6623 ; free virtual = 41242 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2075.172 ; gain = 31.625 ; free physical = 6543 ; free virtual = 41162 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2075.172 ; gain = 31.625 ; free physical = 6543 ; free virtual = 41163 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.586 ; gain = 62.086 ; free physical = 6478 ; free virtual = 41097 Phase 3 Initial Routing Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6440 ; free virtual = 41059 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6420 ; free virtual = 41039 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6410 ; free virtual = 41029 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6410 ; free virtual = 41029 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6410 ; free virtual = 41029 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6405 ; free virtual = 41025 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 6405 ; free virtual = 41024 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.586 ; gain = 62.086 ; free physical = 6384 ; free virtual = 41003 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.586 ; gain = 62.086 ; free physical = 6377 ; free virtual = 40996 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.586 ; gain = 62.086 ; free physical = 6376 ; free virtual = 40995 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.586 ; gain = 62.086 ; free physical = 6373 ; free virtual = 40992 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.586 ; gain = 62.086 ; free physical = 6372 ; free virtual = 40990 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.586 ; gain = 62.086 ; free physical = 6371 ; free virtual = 40989 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2078.965 ; gain = 60.711 ; free physical = 6323 ; free virtual = 40942 Phase 3 Initial Routing Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.586 ; gain = 62.086 ; free physical = 6313 ; free virtual = 40931 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.586 ; gain = 64.086 ; free physical = 6309 ; free virtual = 40928 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.586 ; gain = 64.086 ; free physical = 6300 ; free virtual = 40919 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.586 ; gain = 64.086 ; free physical = 6346 ; free virtual = 40965 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2126.375 ; gain = 134.891 ; free physical = 6347 ; free virtual = 40966 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6339 ; free virtual = 40958 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. Writing placer database... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 6294 ; free virtual = 40913 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 6319 ; free virtual = 40939 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 6319 ; free virtual = 40939 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 6319 ; free virtual = 40939 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 6319 ; free virtual = 40938 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 6320 ; free virtual = 40940 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6282 ; free virtual = 40902 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 6289 ; free virtual = 40909 Phase 8 Verifying routed nets Verification completed successfully Writing XDEF routing. Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 6286 ; free virtual = 40906 Phase 9 Depositing Routes Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6281 ; free virtual = 40902 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6281 ; free virtual = 40902 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6281 ; free virtual = 40902 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6280 ; free virtual = 40902 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6279 ; free virtual = 40901 Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 6283 ; free virtual = 40905 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 6319 ; free virtual = 40942 Routing Is Done. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 7 Route finalize Write XDEF Complete: Time (s): cpu = 00:00:00.70 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2126.375 ; gain = 0.000 ; free physical = 6316 ; free virtual = 40938 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:45 . Memory (MB): peak = 2121.754 ; gain = 135.516 ; free physical = 6315 ; free virtual = 40937 Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 6286 ; free virtual = 40908 Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6286 ; free virtual = 40908 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6288 ; free virtual = 40911 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6289 ; free virtual = 40911 Writing placer database... INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.227 ; gain = 51.680 ; free physical = 6302 ; free virtual = 40925 Routing Is Done. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2134.016 ; gain = 90.469 ; free physical = 6300 ; free virtual = 40919 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2121.754 ; gain = 0.000 ; free physical = 6222 ; free virtual = 40843 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2134.016 ; gain = 0.000 ; free physical = 6212 ; free virtual = 40835 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Routing Task INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.203 ; gain = 0.000 ; free physical = 5880 ; free virtual = 40500 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 5927 ; free virtual = 40547 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 5935 ; free virtual = 40555 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 5936 ; free virtual = 40556 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 5935 ; free virtual = 40555 Phase 2 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: bitstream_checks Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 5935 ; free virtual = 40555 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 5936 ; free virtual = 40556 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.246 ; gain = 499.562 ; free physical = 5936 ; free virtual = 40556 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2004.152 ; gain = 456.203 ; free physical = 5819 ; free virtual = 40439 Phase 1.3 Build Placer Netlist Model INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design Loading data files... Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 5739 ; free virtual = 40361 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 5511 ; free virtual = 40133 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 5511 ; free virtual = 40133 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.824 ; gain = 42.668 ; free physical = 5520 ; free virtual = 40142 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.812 ; gain = 48.656 ; free physical = 5438 ; free virtual = 40060 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.812 ; gain = 48.656 ; free physical = 5432 ; free virtual = 40054 Loading data files... Loading data files... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.152 ; gain = 456.203 ; free physical = 5393 ; free virtual = 40014 Phase 1.4 Constrain Clocks/Macros Loading data files... Writing bitstream ./design.bit... Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.152 ; gain = 456.203 ; free physical = 5347 ; free virtual = 39969 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.117 ; gain = 61.961 ; free physical = 5343 ; free virtual = 39965 Phase 3 Initial Routing Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.152 ; gain = 456.203 ; free physical = 5339 ; free virtual = 39964 Phase 2 Global Placement Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.117 ; gain = 62.961 ; free physical = 5361 ; free virtual = 39987 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.117 ; gain = 62.961 ; free physical = 5386 ; free virtual = 40012 Phase 4 Rip-up And Reroute | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.117 ; gain = 62.961 ; free physical = 5391 ; free virtual = 40016 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.117 ; gain = 62.961 ; free physical = 5392 ; free virtual = 40018 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.117 ; gain = 62.961 ; free physical = 5397 ; free virtual = 40023 Phase 6 Post Hold Fix | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.117 ; gain = 62.961 ; free physical = 5417 ; free virtual = 40043 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.117 ; gain = 62.961 ; free physical = 5574 ; free virtual = 40199 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.117 ; gain = 64.961 ; free physical = 5569 ; free virtual = 40195 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.117 ; gain = 64.961 ; free physical = 5528 ; free virtual = 40154 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.117 ; gain = 64.961 ; free physical = 5561 ; free virtual = 40187 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2129.906 ; gain = 135.766 ; free physical = 5560 ; free virtual = 40186 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2129.906 ; gain = 0.000 ; free physical = 5452 ; free virtual = 40081 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Loading route data... Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:09:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2452.867 ; gain = 344.105 ; free physical = 5054 ; free virtual = 39681 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:09:37 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Phase 1 Build RT Design | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 5974 ; free virtual = 40601 Number of configuration frames: 9996 DONE Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 5944 ; free virtual = 40570 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 5933 ; free virtual = 40560 touch build/specimen_002/OK Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5928 ; free virtual = 40555 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5831 ; free virtual = 40457 Phase 3.2 Commit Most Macros & LUTRAMs Number of Nodes with overlaps = 0 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5787 ; free virtual = 40414 Phase 2 Router Initialization | Checksum: 12e953610 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5790 ; free virtual = 40417 Phase 3 Initial Routing Phase 3.3 Area Swap Optimization Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5716 ; free virtual = 40342 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1343.070 ; gain = 247.152 ; free physical = 5713 ; free virtual = 40340 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5724 ; free virtual = 40351 Phase 4 Rip-up And Reroute | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5727 ; free virtual = 40354 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5729 ; free virtual = 40356 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5730 ; free virtual = 40356 Phase 6 Post Hold Fix | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5735 ; free virtual = 40361 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5699 ; free virtual = 40325 Phase 8 Verifying routed nets Verification completed successfully Phase 3.3 Area Swap Optimization | Checksum: 23216312d Phase 8 Verifying routed nets | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5693 ; free virtual = 40319 Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5693 ; free virtual = 40319 Phase 9 Depositing Routes Phase 3.4 Pipeline Register Optimization Phase 9 Depositing Routes | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5663 ; free virtual = 40289 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 5720 ; free virtual = 40347 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2141.023 ; gain = 56.477 ; free physical = 5718 ; free virtual = 40344 Writing placer database... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5674 ; free virtual = 40301 Phase 3.5 Small Shape Detail Placement Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2141.023 ; gain = 0.000 ; free physical = 5627 ; free virtual = 40256 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5680 ; free virtual = 40310 Phase 3.6 Re-assign LUT pins Creating bitstream... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1351.102 ; gain = 255.184 ; free physical = 5684 ; free virtual = 40314 --------------------------------------------------------------------------------- Loading site data... Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5680 ; free virtual = 40311 Phase 3.7 Pipeline Register Optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5647 ; free virtual = 40278 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1351.102 ; gain = 255.184 ; free physical = 5632 ; free virtual = 40263 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading route data... Phase 3 Detail Placement | Checksum: 181723f81 Processing options... Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5628 ; free virtual = 40259 Creating bitmap... Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5589 ; free virtual = 40220 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5502 ; free virtual = 40133 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5490 ; free virtual = 40121 Phase 4.4 Final Placement Cleanup Loading site data... Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5528 ; free virtual = 40159 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5478 ; free virtual = 40109 Loading route data... Processing options... Creating bitmap... Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2092.195 ; gain = 544.246 ; free physical = 5446 ; free virtual = 40077 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.195 ; gain = 624.949 ; free physical = 5445 ; free virtual = 40076 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:09:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 2450.871 ; gain = 343.105 ; free physical = 5432 ; free virtual = 40063 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:09:45 2019... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 5426 ; free virtual = 40057 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 6555 ; free virtual = 41190 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 6555 ; free virtual = 41190 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 6574 ; free virtual = 41209 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 6592 ; free virtual = 41227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 6583 ; free virtual = 41218 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 6581 ; free virtual = 41216 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 6581 ; free virtual = 41216 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.078 ; gain = 263.160 ; free physical = 6581 ; free virtual = 41216 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1359.086 ; gain = 263.160 ; free physical = 6583 ; free virtual = 41217 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:09:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading site data... 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2452.871 ; gain = 341.105 ; free physical = 6698 ; free virtual = 41337 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:09:50 2019... INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:09:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 2465.121 ; gain = 331.105 ; free physical = 7867 ; free virtual = 42510 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:09:52 2019... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. #of segments: 2 #of bits: 388 #of tags: 1 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:09:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2462.551 ; gain = 336.176 ; free physical = 8747 ; free virtual = 43395 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:09:55 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:10:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 2461.859 ; gain = 340.105 ; free physical = 9779 ; free virtual = 44433 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:10:00 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7052 Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:10:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:41 ; elapsed = 00:00:32 . Memory (MB): peak = 2470.012 ; gain = 340.105 ; free physical = 11299 ; free virtual = 45957 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:10:06 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 Writing bitstream ./design.bit... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7189 Phase 1 Build RT Design | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 12252 ; free virtual = 46916 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2063.922 ; gain = 99.656 ; free physical = 12227 ; free virtual = 46891 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2063.922 ; gain = 99.656 ; free physical = 12226 ; free virtual = 46891 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 12199 ; free virtual = 46863 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 12159 ; free virtual = 46823 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 12155 ; free virtual = 46820 Phase 4 Rip-up And Reroute | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 12155 ; free virtual = 46820 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 12155 ; free virtual = 46820 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 12155 ; free virtual = 46819 Phase 6 Post Hold Fix | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 12155 ; free virtual = 46819 Phase 7 Route finalize INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:10:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2474.129 ; gain = 333.105 ; free physical = 12158 ; free virtual = 46823 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:10:12 2019... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 12172 ; free virtual = 46836 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 12170 ; free virtual = 46834 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 12170 ; free virtual = 46834 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 12204 ; free virtual = 46868 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2111.766 ; gain = 179.516 ; free physical = 12206 ; free virtual = 46870 Writing placer database... Command: synth_design -top top Writing XDEF routing. Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2111.766 ; gain = 0.000 ; free physical = 12274 ; free virtual = 46940 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 13102 ; free virtual = 47767 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 13049 ; free virtual = 47714 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: Helper process launched with PID 7274 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2054.930 ; gain = 121.668 ; free physical = 13013 ; free virtual = 47678 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.918 ; gain = 127.656 ; free physical = 12957 ; free virtual = 47622 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.918 ; gain = 127.656 ; free physical = 12957 ; free virtual = 47622 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.973 ; gain = 133.711 ; free physical = 12977 ; free virtual = 47642 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 133.711 ; free physical = 12954 ; free virtual = 47619 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 133.711 ; free physical = 12940 ; free virtual = 47605 Phase 4 Rip-up And Reroute | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 133.711 ; free physical = 12940 ; free virtual = 47605 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 133.711 ; free physical = 12940 ; free virtual = 47605 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 133.711 ; free physical = 12939 ; free virtual = 47605 Phase 6 Post Hold Fix | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 133.711 ; free physical = 12939 ; free virtual = 47605 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.973 ; gain = 133.711 ; free physical = 12882 ; free virtual = 47547 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.973 ; gain = 136.711 ; free physical = 12879 ; free virtual = 47544 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.973 ; gain = 136.711 ; free physical = 12878 ; free virtual = 47543 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.973 ; gain = 136.711 ; free physical = 12907 ; free virtual = 47572 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2108.762 ; gain = 207.516 ; free physical = 12912 ; free virtual = 47577 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2108.762 ; gain = 0.000 ; free physical = 12941 ; free virtual = 47608 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 13042 ; free virtual = 47708 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7370 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 13050 ; free virtual = 47716 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 13047 ; free virtual = 47714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 13042 ; free virtual = 47708 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 12923 ; free virtual = 47588 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 12922 ; free virtual = 47588 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7420 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 12597 ; free virtual = 47263 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 12369 ; free virtual = 47035 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 12361 ; free virtual = 47027 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 12360 ; free virtual = 47026 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 12358 ; free virtual = 47024 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7467 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11933 ; free virtual = 46599 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11934 ; free virtual = 46600 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11928 ; free virtual = 46594 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 11910 ; free virtual = 46576 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11804 ; free virtual = 46470 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11803 ; free virtual = 46469 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11799 ; free virtual = 46465 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11798 ; free virtual = 46464 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11797 ; free virtual = 46463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11797 ; free virtual = 46463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11794 ; free virtual = 46460 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11792 ; free virtual = 46458 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 11797 ; free virtual = 46463 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 11799 ; free virtual = 46465 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading site data... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11491 ; free virtual = 46157 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2130.426 ; gain = 38.230 ; free physical = 11310 ; free virtual = 45976 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2136.414 ; gain = 44.219 ; free physical = 11255 ; free virtual = 45921 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2136.414 ; gain = 44.219 ; free physical = 11254 ; free virtual = 45920 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11231 ; free virtual = 45897 --------------------------------------------------------------------------------- Creating bitstream... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11243 ; free virtual = 45909 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11235 ; free virtual = 45901 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] --------------------------------------------------------------------------------- Start IO Insertion WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] INFO: Launching helper process for spawning children vivado processes WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Helper process launched with PID 7520 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11246 ; free virtual = 45913 --------------------------------------------------------------------------------- 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1396.684 ; gain = 313.797 ; free physical = 11250 ; free virtual = 45916 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11251 ; free virtual = 45917 Phase 3 Initial Routing Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11245 ; free virtual = 45911 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11247 ; free virtual = 45914 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11217 ; free virtual = 45883 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11175 ; free virtual = 45841 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 11208 ; free virtual = 45874 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 11207 ; free virtual = 45874 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11203 ; free virtual = 45869 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11202 ; free virtual = 45869 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11202 ; free virtual = 45869 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11202 ; free virtual = 45869 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11202 ; free virtual = 45868 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading site data... WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:16] Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11198 ; free virtual = 45864 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11196 ; free virtual = 45863 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11190 ; free virtual = 45856 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 62.273 ; free physical = 11224 ; free virtual = 45891 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:45 . Memory (MB): peak = 2193.258 ; gain = 101.062 ; free physical = 11223 ; free virtual = 45889 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11203 ; free virtual = 45870 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11202 ; free virtual = 45869 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11196 ; free virtual = 45863 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11194 ; free virtual = 45861 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11190 ; free virtual = 45857 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11189 ; free virtual = 45857 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11188 ; free virtual = 45856 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11182 ; free virtual = 45850 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 11184 ; free virtual = 45851 Loading route data... Processing options... Creating bitmap... Writing placer database... INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 11122 ; free virtual = 45796 --------------------------------------------------------------------------------- Creating bitstream... Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 11080 ; free virtual = 45760 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 11080 ; free virtual = 45760 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 11074 ; free virtual = 45760 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing XDEF routing. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Writing XDEF routing logical nets. Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Writing XDEF routing special nets. Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.258 ; gain = 0.000 ; free physical = 11122 ; free virtual = 45816 INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11055 ; free virtual = 45750 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11051 ; free virtual = 45724 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11048 ; free virtual = 45721 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10987 ; free virtual = 45662 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1396.688 ; gain = 313.797 ; free physical = 10885 ; free virtual = 45561 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 10930 ; free virtual = 45607 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 11098 ; free virtual = 45775 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 11098 ; free virtual = 45775 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7646 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:10:36 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2453.871 ; gain = 342.105 ; free physical = 10949 ; free virtual = 45625 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:10:36 2019... Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 11009 ; free virtual = 45686 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 11734 ; free virtual = 46411 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 11725 ; free virtual = 46402 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11742 ; free virtual = 46419 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:10:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2450.867 ; gain = 342.105 ; free physical = 11846 ; free virtual = 46525 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:10:37 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- touch build/specimen_003/OK Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 12773 ; free virtual = 47470 --------------------------------------------------------------------------------- GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12762 ; free virtual = 47460 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12768 ; free virtual = 47465 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12767 ; free virtual = 47464 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12767 ; free virtual = 47464 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12766 ; free virtual = 47463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12766 ; free virtual = 47463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12765 ; free virtual = 47463 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 12785 ; free virtual = 47464 Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 12785 ; free virtual = 47464 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12785 ; free virtual = 47463 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 12788 ; free virtual = 47467 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 12703 ; free virtual = 47402 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 12639 ; free virtual = 47337 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 12583 ; free virtual = 47261 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_A bound to: 18'b000000000000000000 Start Loading Part and Timing Information --------------------------------------------------------------------------------- Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Loading part: xc7z020clg400-1 Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 12586 ; free virtual = 47264 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5227] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12564 ; free virtual = 47243 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 12469 ; free virtual = 47152 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 12470 ; free virtual = 47149 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 12468 ; free virtual = 47147 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12448 ; free virtual = 47127 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 12447 ; free virtual = 47126 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12446 ; free virtual = 47125 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12425 ; free virtual = 47104 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12418 ; free virtual = 47097 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12404 ; free virtual = 47083 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 12401 ; free virtual = 47080 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12401 ; free virtual = 47080 Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12396 ; free virtual = 47075 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12396 ; free virtual = 47075 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12387 ; free virtual = 47066 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 12388 ; free virtual = 47067 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 12374 ; free virtual = 47053 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 12202 ; free virtual = 46881 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12200 ; free virtual = 46879 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12199 ; free virtual = 46878 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12198 ; free virtual = 46877 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12198 ; free virtual = 46877 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12198 ; free virtual = 46877 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12197 ; free virtual = 46876 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12197 ; free virtual = 46876 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12196 ; free virtual = 46875 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 12195 ; free virtual = 46874 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Project 1-571] Translating synthesized netlist Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 12184 ; free virtual = 46862 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 12168 ; free virtual = 46847 Phase 2 Final Placement Cleanup INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 12160 ; free virtual = 46839 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 12191 ; free virtual = 46870 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 12194 ; free virtual = 46872 --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-570] Preparing netlist for logic optimization Ending Placer Task | Checksum: 110ed1b10 Command: report_drc (run_mandatory_drcs) for: placer_checks Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 12188 ; free virtual = 46867 INFO: [DRC 23-27] Running DRC with 8 threads 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 12186 ; free virtual = 46865 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 12037 ; free virtual = 46716 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 11983 ; free virtual = 46661 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1351.070 ; gain = 255.152 ; free physical = 11985 ; free virtual = 46664 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 11992 ; free virtual = 46671 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 11896 ; free virtual = 46576 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 11888 ; free virtual = 46567 --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 11752 ; free virtual = 46431 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.203 ; gain = 0.000 ; free physical = 11621 ; free virtual = 46304 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11592 ; free virtual = 46271 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11590 ; free virtual = 46269 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11590 ; free virtual = 46269 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11590 ; free virtual = 46269 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11590 ; free virtual = 46269 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11591 ; free virtual = 46270 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 507.562 ; free physical = 11590 ; free virtual = 46270 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1359.102 ; gain = 263.184 ; free physical = 11415 ; free virtual = 46095 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1359.102 ; gain = 263.184 ; free physical = 11346 ; free virtual = 46025 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 11259 ; free virtual = 45938 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 11273 ; free virtual = 45952 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 11214 ; free virtual = 45893 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11182 ; free virtual = 45861 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11241 ; free virtual = 45920 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 11199 ; free virtual = 45878 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 11197 ; free virtual = 45876 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11185 ; free virtual = 45864 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11183 ; free virtual = 45862 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11180 ; free virtual = 45859 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11179 ; free virtual = 45859 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11179 ; free virtual = 45858 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11178 ; free virtual = 45858 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11178 ; free virtual = 45858 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11177 ; free virtual = 45856 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 11176 ; free virtual = 45856 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11131 ; free virtual = 45811 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11126 ; free virtual = 45805 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11102 ; free virtual = 45781 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11089 ; free virtual = 45768 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11082 ; free virtual = 45761 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11049 ; free virtual = 45728 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11039 ; free virtual = 45718 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1367.078 ; gain = 271.160 ; free physical = 11020 ; free virtual = 45700 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1367.086 ; gain = 271.160 ; free physical = 11018 ; free virtual = 45697 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 10964 ; free virtual = 45644 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.207 ; gain = 0.000 ; free physical = 10691 ; free virtual = 45371 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 10644 ; free virtual = 45323 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 10636 ; free virtual = 45315 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 10636 ; free virtual = 45315 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 10635 ; free virtual = 45314 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 10635 ; free virtual = 45314 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 10636 ; free virtual = 45315 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 507.562 ; free physical = 10636 ; free virtual = 45315 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1551.953 ; gain = 0.000 ; free physical = 10573 ; free virtual = 45252 Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1551.953 ; gain = 0.000 ; free physical = 10550 ; free virtual = 45233 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 10595 ; free virtual = 45278 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 10758 ; free virtual = 45442 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10787 ; free virtual = 45471 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10613 ; free virtual = 45297 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10612 ; free virtual = 45295 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10609 ; free virtual = 45292 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10605 ; free virtual = 45289 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10605 ; free virtual = 45288 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10604 ; free virtual = 45288 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10602 ; free virtual = 45285 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10600 ; free virtual = 45283 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 10601 ; free virtual = 45284 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 10556 ; free virtual = 45239 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8017 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:11:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2532.363 ; gain = 339.105 ; free physical = 10545 ; free virtual = 45229 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:11:00 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 10625 ; free virtual = 45308 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 10780 ; free virtual = 45463 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Netlist 29-28] Unisim Transformation completed in 5 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8114 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 11265 ; free virtual = 45949 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 11259 ; free virtual = 45944 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1296e3a58 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 11259 ; free virtual = 45944 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 11178 ; free virtual = 45862 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 11149 ; free virtual = 45834 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 11144 ; free virtual = 45829 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 11139 ; free virtual = 45823 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 11138 ; free virtual = 45823 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 11147 ; free virtual = 45832 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 11144 ; free virtual = 45828 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 11144 ; free virtual = 45828 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10978 ; free virtual = 45663 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 10548 ; free virtual = 45232 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10569 ; free virtual = 45254 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10559 ; free virtual = 45244 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10559 ; free virtual = 45244 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 10553 ; free virtual = 45238 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10552 ; free virtual = 45237 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 10548 ; free virtual = 45233 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 10545 ; free virtual = 45231 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 10542 ; free virtual = 45227 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 10542 ; free virtual = 45227 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 10538 ; free virtual = 45223 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 10538 ; free virtual = 45223 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 10461 ; free virtual = 45146 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 10133 ; free virtual = 44818 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 10153 ; free virtual = 44838 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 10146 ; free virtual = 44831 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 10145 ; free virtual = 44830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 10142 ; free virtual = 44827 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2003.156 ; gain = 451.203 ; free physical = 9968 ; free virtual = 44653 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 9695 ; free virtual = 44380 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 451.203 ; free physical = 9532 ; free virtual = 44217 Phase 1.4 Constrain Clocks/Macros INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.234 ; gain = 0.000 ; free physical = 9511 ; free virtual = 44196 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 451.203 ; free physical = 9508 ; free virtual = 44193 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 451.203 ; free physical = 9477 ; free virtual = 44162 Phase 2 Global Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 9470 ; free virtual = 44155 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 9471 ; free virtual = 44156 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 9471 ; free virtual = 44156 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 9470 ; free virtual = 44155 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 9465 ; free virtual = 44154 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 9468 ; free virtual = 44153 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.277 ; gain = 577.562 ; free physical = 9466 ; free virtual = 44151 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9399 ; free virtual = 44084 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9361 ; free virtual = 44046 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9353 ; free virtual = 44038 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1547.859 ; gain = 0.000 ; free physical = 9315 ; free virtual = 44000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.67 . Memory (MB): peak = 1547.859 ; gain = 0.000 ; free physical = 9305 ; free virtual = 43990 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9288 ; free virtual = 43973 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9287 ; free virtual = 43972 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9285 ; free virtual = 43970 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9284 ; free virtual = 43969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9284 ; free virtual = 43969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9280 ; free virtual = 43965 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9280 ; free virtual = 43965 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Starting Routing Task Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9278 ; free virtual = 43963 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 9277 ; free virtual = 43962 INFO: [Project 1-571] Translating synthesized netlist Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 9022 ; free virtual = 43707 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 8970 ; free virtual = 43655 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8966 ; free virtual = 43651 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8956 ; free virtual = 43641 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 8949 ; free virtual = 43634 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8949 ; free virtual = 43634 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8885 ; free virtual = 43570 Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8878 ; free virtual = 43564 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8878 ; free virtual = 43563 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8877 ; free virtual = 43563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8877 ; free virtual = 43563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8878 ; free virtual = 43563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8878 ; free virtual = 43563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8878 ; free virtual = 43563 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8878 ; free virtual = 43564 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 8880 ; free virtual = 43566 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e1594fd1 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8880 ; free virtual = 43565 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8882 ; free virtual = 43567 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-571] Translating synthesized netlist Phase 1.4 Constrain Clocks/Macros | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8878 ; free virtual = 43563 Phase 1 Placer Initialization | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8874 ; free virtual = 43559 Phase 2 Global Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8868 ; free virtual = 43553 Phase 3.4 Pipeline Register Optimization INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8854 ; free virtual = 43540 Phase 3.5 Small Shape Detail Placement WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9490 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8802 ; free virtual = 43487 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8788 ; free virtual = 43474 Phase 3.7 Pipeline Register Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 8819 ; free virtual = 43504 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8820 ; free virtual = 43505 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8812 ; free virtual = 43497 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8801 ; free virtual = 43487 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8792 ; free virtual = 43477 Phase 4.3 Placer Reporting Phase 2 Global Placement | Checksum: 27094be7a Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8773 ; free virtual = 43458 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8764 ; free virtual = 43450 Phase 3.2 Commit Most Macros & LUTRAMs Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8760 ; free virtual = 43445 Phase 4.4 Final Placement Cleanup Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 215570181 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8760 ; free virtual = 43445 Phase 3.3 Area Swap Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.3 Area Swap Optimization | Checksum: 1ef31df4c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8744 ; free virtual = 43429 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b8e63fb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8740 ; free virtual = 43425 Phase 3.5 Small Shape Detail Placement Starting Placer Task Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8737 ; free virtual = 43422 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 8733 ; free virtual = 43418 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 8733 ; free virtual = 43418 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8704 ; free virtual = 43389 Phase 3.5 Small Shape Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8753 ; free virtual = 43438 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8749 ; free virtual = 43434 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8748 ; free virtual = 43433 Phase 3 Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8745 ; free virtual = 43430 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8736 ; free virtual = 43421 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 547.250 ; free physical = 8736 ; free virtual = 43421 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 8734 ; free virtual = 43419 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8728 ; free virtual = 43413 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8726 ; free virtual = 43411 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8723 ; free virtual = 43408 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8720 ; free virtual = 43405 Ending Placer Task | Checksum: 146bf3d33 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8733 ; free virtual = 43418 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 8734 ; free virtual = 43419 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1401.691 ; gain = 318.797 ; free physical = 8736 ; free virtual = 43421 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 107963fbc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.074 ; gain = 50.668 ; free physical = 8668 ; free virtual = 43354 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.723 ; gain = 0.000 ; free physical = 8678 ; free virtual = 43363 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1465.723 ; gain = 0.000 ; free physical = 8678 ; free virtual = 43363 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 1 Build RT Design | Checksum: c47cd168 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2055.930 ; gain = 119.668 ; free physical = 8680 ; free virtual = 43365 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints | Checksum: 107963fbc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8677 ; free virtual = 43362 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 107963fbc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8668 ; free virtual = 43353 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: c47cd168 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2061.918 ; gain = 125.656 ; free physical = 8647 ; free virtual = 43332 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: c47cd168 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2061.918 ; gain = 125.656 ; free physical = 8647 ; free virtual = 43332 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 8625 ; free virtual = 43310 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully Phase 3 Initial Routing INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 621f9429 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 8591 ; free virtual = 43276 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 8597 ; free virtual = 43282 Phase 4 Rip-up And Reroute | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 8596 ; free virtual = 43281 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 8595 ; free virtual = 43281 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 8595 ; free virtual = 43280 Phase 6 Post Hold Fix | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 8594 ; free virtual = 43280 Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 8578 ; free virtual = 43264 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2071.973 ; gain = 135.711 ; free physical = 8576 ; free virtual = 43261 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1481dbb17 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2071.973 ; gain = 135.711 ; free physical = 8576 ; free virtual = 43261 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2071.973 ; gain = 135.711 ; free physical = 8606 ; free virtual = 43291 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.762 ; gain = 206.516 ; free physical = 8605 ; free virtual = 43290 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8592 ; free virtual = 43277 Phase 3 Initial Routing Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 8586 ; free virtual = 43273 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8555 ; free virtual = 43241 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8542 ; free virtual = 43228 Phase 4 Rip-up And Reroute | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8534 ; free virtual = 43219 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8522 ; free virtual = 43207 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8505 ; free virtual = 43191 Phase 6 Post Hold Fix | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8495 ; free virtual = 43180 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8504 ; free virtual = 43189 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8518 ; free virtual = 43204 Phase 9 Depositing Routes Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 1c2f462cb Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8543 ; free virtual = 43228 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 8586 ; free virtual = 43271 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 2218.281 ; gain = 165.891 ; free physical = 8586 ; free virtual = 43271 Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 8457 ; free virtual = 43160 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 109653c4d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2056.934 ; gain = 120.668 ; free physical = 8409 ; free virtual = 43113 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 109653c4d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 8394 ; free virtual = 43100 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 109653c4d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 8394 ; free virtual = 43100 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 8325 ; free virtual = 43033 Phase 3 Initial Routing Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 8307 ; free virtual = 43017 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 8309 ; free virtual = 43020 Phase 4 Rip-up And Reroute | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 8309 ; free virtual = 43020 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 8309 ; free virtual = 43020 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 8309 ; free virtual = 43020 Phase 6 Post Hold Fix | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 8309 ; free virtual = 43020 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.281 ; gain = 0.000 ; free physical = 8330 ; free virtual = 43044 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 8330 ; free virtual = 43044 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.977 ; gain = 134.711 ; free physical = 8329 ; free virtual = 43043 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.977 ; gain = 134.711 ; free physical = 8329 ; free virtual = 43043 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.977 ; gain = 134.711 ; free physical = 8361 ; free virtual = 43076 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2109.766 ; gain = 205.516 ; free physical = 8361 ; free virtual = 43075 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2109.766 ; gain = 0.000 ; free physical = 8325 ; free virtual = 43041 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design.dcp' has been generated. WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:16] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 7521 ; free virtual = 42210 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7506 ; free virtual = 42196 --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7497 ; free virtual = 42186 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 7488 ; free virtual = 42178 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 504.531 ; free physical = 7395 ; free virtual = 42084 Phase 1.3 Build Placer Netlist Model WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 7059 ; free virtual = 41748 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.211 ; gain = 0.000 ; free physical = 6510 ; free virtual = 41200 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 6541 ; free virtual = 41230 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 6548 ; free virtual = 41237 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 6547 ; free virtual = 41236 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 6547 ; free virtual = 41236 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 6546 ; free virtual = 41236 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 6546 ; free virtual = 41236 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 6546 ; free virtual = 41236 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.254 ; gain = 499.562 ; free physical = 6546 ; free virtual = 41236 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 6419 ; free virtual = 41108 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 6412 ; free virtual = 41101 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 6412 ; free virtual = 41101 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 6412 ; free virtual = 41101 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 6411 ; free virtual = 41101 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 6409 ; free virtual = 41099 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 6409 ; free virtual = 41099 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 504.531 ; free physical = 6373 ; free virtual = 41063 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 504.531 ; free physical = 6388 ; free virtual = 41077 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 504.531 ; free physical = 6402 ; free virtual = 41092 Phase 2 Final Placement Cleanup INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 504.531 ; free physical = 6368 ; free virtual = 41057 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.172 ; gain = 44.668 ; free physical = 6358 ; free virtual = 41047 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 6314 ; free virtual = 41003 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 6311 ; free virtual = 41001 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 504.531 ; free physical = 6303 ; free virtual = 40992 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 6297 ; free virtual = 40986 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 6272 ; free virtual = 40961 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 63.961 ; free physical = 6205 ; free virtual = 40895 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 63.961 ; free physical = 6205 ; free virtual = 40895 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 63.961 ; free physical = 6205 ; free virtual = 40895 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 63.961 ; free physical = 6206 ; free virtual = 40895 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 63.961 ; free physical = 6205 ; free virtual = 40895 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 63.961 ; free physical = 6205 ; free virtual = 40894 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.465 ; gain = 63.961 ; free physical = 6186 ; free virtual = 40875 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 6184 ; free virtual = 40873 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 6183 ; free virtual = 40872 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 6212 ; free virtual = 40902 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2128.254 ; gain = 137.766 ; free physical = 6212 ; free virtual = 40901 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 6174 ; free virtual = 40866 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 6216 ; free virtual = 40910 --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Running DRC as a precondition to command write_bitstream Phase 1 Build RT Design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 6414 ; free virtual = 41108 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6301 ; free virtual = 40995 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2063.926 ; gain = 44.668 ; free physical = 6285 ; free virtual = 40979 Loading site data... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.914 ; gain = 49.656 ; free physical = 6250 ; free virtual = 40944 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.914 ; gain = 49.656 ; free physical = 6248 ; free virtual = 40942 Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 6199 ; free virtual = 40894 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6182 ; free virtual = 40876 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6167 ; free virtual = 40861 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6163 ; free virtual = 40858 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6160 ; free virtual = 40854 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6153 ; free virtual = 40847 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6149 ; free virtual = 40844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6148 ; free virtual = 40842 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 6140 ; free virtual = 40834 Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 6140 ; free virtual = 40834 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6135 ; free virtual = 40829 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6121 ; free virtual = 40815 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6121 ; free virtual = 40815 Phase 5 Delay and Skew Optimization INFO: [Project 1-571] Translating synthesized netlist Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6121 ; free virtual = 40815 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6114 ; free virtual = 40808 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6116 ; free virtual = 40810 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6128 ; free virtual = 40822 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.969 ; gain = 64.711 ; free physical = 6129 ; free virtual = 40823 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.969 ; gain = 64.711 ; free physical = 6175 ; free virtual = 40869 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.969 ; gain = 64.711 ; free physical = 6212 ; free virtual = 40906 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2122.758 ; gain = 135.516 ; free physical = 6213 ; free virtual = 40907 Creating bitstream... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2122.758 ; gain = 0.000 ; free physical = 6153 ; free virtual = 40849 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:12:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 2452.867 ; gain = 342.105 ; free physical = 6138 ; free virtual = 40833 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:12:00 2019... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. touch build/specimen_003/OK INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:12:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 2452.871 ; gain = 343.105 ; free physical = 6732 ; free virtual = 41435 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:12:07 2019... Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 30 #of tags: 3 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 Phase 1 Build RT Design | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.961 ; gain = 41.668 ; free physical = 7572 ; free virtual = 42276 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.949 ; gain = 47.656 ; free physical = 7538 ; free virtual = 42242 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.949 ; gain = 47.656 ; free physical = 7538 ; free virtual = 42242 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.254 ; gain = 60.961 ; free physical = 7504 ; free virtual = 42209 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7457 ; free virtual = 42162 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7457 ; free virtual = 42161 Phase 4 Rip-up And Reroute | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7457 ; free virtual = 42161 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7456 ; free virtual = 42161 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7456 ; free virtual = 42160 Phase 6 Post Hold Fix | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7456 ; free virtual = 42160 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7448 ; free virtual = 42153 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2091.254 ; gain = 64.961 ; free physical = 7447 ; free virtual = 42151 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2091.254 ; gain = 64.961 ; free physical = 7446 ; free virtual = 42151 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2091.254 ; gain = 64.961 ; free physical = 7484 ; free virtual = 42189 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2130.043 ; gain = 135.766 ; free physical = 7484 ; free virtual = 42189 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.60 . Memory (MB): peak = 2130.043 ; gain = 0.000 ; free physical = 7468 ; free virtual = 42176 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:49 . Memory (MB): peak = 1467.254 ; gain = 384.367 ; free physical = 7437 ; free virtual = 42142 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading site data... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.957 ; gain = 0.000 ; free physical = 7314 ; free virtual = 42020 Loading route data... Processing options... Creating bitmap... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1547.957 ; gain = 0.000 ; free physical = 7297 ; free virtual = 42003 Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... Loading site data... Phase 1 Build RT Design | Checksum: 1a640bfe0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 6982 ; free virtual = 41687 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1a640bfe0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 6917 ; free virtual = 41622 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a640bfe0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 6917 ; free virtual = 41622 Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 17f6b07bf Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 6964 ; free virtual = 41673 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7156 ; free virtual = 41866 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7174 ; free virtual = 41883 Phase 4 Rip-up And Reroute | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7176 ; free virtual = 41886 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7180 ; free virtual = 41890 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7185 ; free virtual = 41894 Phase 6 Post Hold Fix | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7189 ; free virtual = 41898 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2130.102 ; gain = 30.898 ; free physical = 7196 ; free virtual = 41905 Phase 7 Route finalize INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing bitstream ./design.bit... Phase 2.1 Fix Topology Constraints Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2136.090 ; gain = 36.887 ; free physical = 7178 ; free virtual = 41888 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2136.090 ; gain = 36.887 ; free physical = 7178 ; free virtual = 41888 Phase 7 Route finalize | Checksum: 63a0e4fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7172 ; free virtual = 41883 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 63a0e4fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7170 ; free virtual = 41881 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 63a0e4fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7167 ; free virtual = 41881 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 7206 ; free virtual = 41919 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2141.016 ; gain = 48.473 ; free physical = 7216 ; free virtual = 41929 Writing placer database... Writing XDEF routing. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing logical nets. Writing XDEF routing special nets. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7476 ; free virtual = 42191 Phase 3 Initial Routing Write XDEF Complete: Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2141.016 ; gain = 0.000 ; free physical = 7474 ; free virtual = 42190 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7490 ; free virtual = 42204 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7481 ; free virtual = 42194 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7478 ; free virtual = 42192 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7475 ; free virtual = 42189 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7473 ; free virtual = 42187 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7473 ; free virtual = 42187 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7456 ; free virtual = 42169 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7455 ; free virtual = 42168 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7476 ; free virtual = 42190 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.145 ; gain = 54.941 ; free physical = 7508 ; free virtual = 42222 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2192.934 ; gain = 93.730 ; free physical = 7507 ; free virtual = 42221 Writing placer database... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:12:26 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:47 . Memory (MB): peak = 2606.441 ; gain = 388.160 ; free physical = 7278 ; free virtual = 42005 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:12:26 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:12:27 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2463.430 ; gain = 335.176 ; free physical = 7411 ; free virtual = 42138 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:12:27 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 Creating bitstream... touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2192.934 ; gain = 0.000 ; free physical = 9423 ; free virtual = 44160 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... Writing bitstream ./design.bit... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10824 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:12:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2460.863 ; gain = 338.105 ; free physical = 9379 ; free virtual = 44099 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:12:35 2019... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10872 Loading data files... touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 9739 ; free virtual = 44459 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: f351153a Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 9669 ; free virtual = 44389 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Loading site data... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f351153a Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 9632 ; free virtual = 44353 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f351153a Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 9632 ; free virtual = 44353 Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2054.938 ; gain = 121.668 ; free physical = 9605 ; free virtual = 44325 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2059.926 ; gain = 126.656 ; free physical = 9542 ; free virtual = 44262 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2059.926 ; gain = 126.656 ; free physical = 9542 ; free virtual = 44262 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9531 ; free virtual = 44251 Phase 3 Initial Routing Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.980 ; gain = 133.711 ; free physical = 9525 ; free virtual = 44246 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9504 ; free virtual = 44224 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9506 ; free virtual = 44226 Phase 4 Rip-up And Reroute | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9506 ; free virtual = 44226 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9506 ; free virtual = 44226 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9506 ; free virtual = 44226 Phase 6 Post Hold Fix | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9506 ; free virtual = 44226 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9496 ; free virtual = 44216 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 9494 ; free virtual = 44215 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 9495 ; free virtual = 44215 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 9527 ; free virtual = 44248 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2111.766 ; gain = 179.516 ; free physical = 9527 ; free virtual = 44247 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.980 ; gain = 133.711 ; free physical = 9530 ; free virtual = 44250 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.980 ; gain = 133.711 ; free physical = 9523 ; free virtual = 44244 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.980 ; gain = 133.711 ; free physical = 9523 ; free virtual = 44244 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.980 ; gain = 133.711 ; free physical = 9523 ; free virtual = 44244 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.980 ; gain = 133.711 ; free physical = 9523 ; free virtual = 44244 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.980 ; gain = 133.711 ; free physical = 9523 ; free virtual = 44244 Writing placer database... Writing XDEF routing. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 7 Route finalize Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2111.766 ; gain = 0.000 ; free physical = 9528 ; free virtual = 44250 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.980 ; gain = 133.711 ; free physical = 9458 ; free virtual = 44179 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.980 ; gain = 135.711 ; free physical = 9455 ; free virtual = 44175 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.980 ; gain = 135.711 ; free physical = 9454 ; free virtual = 44174 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.980 ; gain = 135.711 ; free physical = 9478 ; free virtual = 44199 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2107.770 ; gain = 206.516 ; free physical = 9468 ; free virtual = 44189 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2107.770 ; gain = 0.000 ; free physical = 9444 ; free virtual = 44166 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.160 ; gain = 455.203 ; free physical = 9421 ; free virtual = 44142 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 9679 ; free virtual = 44404 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 168520de7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2134.074 ; gain = 49.668 ; free physical = 9500 ; free virtual = 44225 Loading site data... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 168520de7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 9444 ; free virtual = 44169 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 168520de7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 9438 ; free virtual = 44163 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1800] Loading route data... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1824] Processing options... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1968] Creating bitmap... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.160 ; gain = 455.203 ; free physical = 9404 ; free virtual = 44129 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.160 ; gain = 455.203 ; free physical = 9427 ; free virtual = 44152 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.160 ; gain = 455.203 ; free physical = 9432 ; free virtual = 44157 Phase 2 Global Placement Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9412 ; free virtual = 44137 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:12:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:34 . Memory (MB): peak = 2471.648 ; gain = 341.605 ; free physical = 9426 ; free virtual = 44151 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:12:46 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 9421 ; free virtual = 44145 Phase 3 Initial Routing INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10277 ; free virtual = 45003 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10252 ; free virtual = 44978 Phase 4 Rip-up And Reroute | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10236 ; free virtual = 44962 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10217 ; free virtual = 44943 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10209 ; free virtual = 44935 Phase 6 Post Hold Fix | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10213 ; free virtual = 44938 Creating bitstream... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Phase 7 Route finalize | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10264 ; free virtual = 44990 Phase 8 Verifying routed nets INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10261 ; free virtual = 44987 Phase 9 Depositing Routes Creating bitstream... Phase 9 Depositing Routes | Checksum: 15eed57fc Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10157 ; free virtual = 44883 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] INFO: [Route 35-16] Router Completed Successfully WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.492 ; gain = 96.086 ; free physical = 10186 ; free virtual = 44912 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] Routing Is Done. WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2219.281 ; gain = 166.891 ; free physical = 10185 ; free virtual = 44911 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading data files... Writing placer database... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10027 ; free virtual = 44763 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10035 ; free virtual = 44773 Phase 3.2 Commit Most Macros & LUTRAMs Writing bitstream ./design.bit... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 9960 ; free virtual = 44706 Phase 3.3 Area Swap Optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10193 ; free virtual = 44943 Phase 3.4 Pipeline Register Optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10146 ; free virtual = 44898 Phase 3.5 Small Shape Detail Placement Writing bitstream ./design.bit... WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:16] Writing XDEF routing. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11726 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2219.281 ; gain = 0.000 ; free physical = 10339 ; free virtual = 45101 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11853 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10463 ; free virtual = 45201 --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10397 ; free virtual = 45141 Phase 3.6 Re-assign LUT pins --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10419 ; free virtual = 45157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 10422 ; free virtual = 45161 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10433 ; free virtual = 45172 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10400 ; free virtual = 45139 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10372 ; free virtual = 45111 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10333 ; free virtual = 45071 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10284 ; free virtual = 45022 Phase 4.3 Placer Reporting INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:12:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2475.121 ; gain = 334.105 ; free physical = 10264 ; free virtual = 45003 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:12:55 2019... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10265 ; free virtual = 45003 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 10368 ; free virtual = 45106 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:12:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 11229 ; free virtual = 45968 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.039 ; gain = 339.105 ; free physical = 11263 ; free virtual = 46002 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:12:56 2019... touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.207 ; gain = 551.250 ; free physical = 11318 ; free virtual = 46056 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.207 ; gain = 631.953 ; free physical = 11319 ; free virtual = 46058 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 12002 ; free virtual = 46740 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12041 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11873 ; free virtual = 46615 --------------------------------------------------------------------------------- Creating bitstream... Creating bitstream... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11718 ; free virtual = 46478 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11717 ; free virtual = 46462 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 11710 ; free virtual = 46456 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 11721 ; free virtual = 46462 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 11610 ; free virtual = 46351 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11627 ; free virtual = 46368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 11578 ; free virtual = 46320 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer --------------------------------------------------------------------------------- Parameter B_INPUT bound to: DIRECT - type: string Start Final Netlist Cleanup Parameter CARRYINREG bound to: 1 - type: integer --------------------------------------------------------------------------------- Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Writing bitstream ./design.bit... INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11680 ; free virtual = 46430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11824 ; free virtual = 46573 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11838 ; free virtual = 46588 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12060 ; free virtual = 46810 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12055 ; free virtual = 46804 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12043 ; free virtual = 46792 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12112 ; free virtual = 46861 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12117 ; free virtual = 46867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12124 ; free virtual = 46873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12123 ; free virtual = 46873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12130 ; free virtual = 46879 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12126 ; free virtual = 46876 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12127 ; free virtual = 46878 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 12128 ; free virtual = 46878 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 12077 ; free virtual = 46827 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 12075 ; free virtual = 46825 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 12070 ; free virtual = 46820 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading data files... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 11864 ; free virtual = 46614 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:13:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.875 ; gain = 342.105 ; free physical = 11756 ; free virtual = 46506 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:13:07 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:13:08 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2453.871 ; gain = 342.105 ; free physical = 11868 ; free virtual = 46618 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:13:08 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 39 #of tags: 2 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 Bitstream size: 4243411 bytes Config size: 1060815 words --------------------------------------------------------------------------------- Number of configuration frames: 9996 DONE Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.992 ; free physical = 13668 ; free virtual = 48418 --------------------------------------------------------------------------------- touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 13337 ; free virtual = 48087 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] Command: synth_design -top top WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 13318 ; free virtual = 48072 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 13317 ; free virtual = 48067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 13240 ; free virtual = 47990 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 13241 ; free virtual = 47991 INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- INFO: Helper process launched with PID 12239 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 13311 ; free virtual = 48061 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 13245 ; free virtual = 47995 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 13231 ; free virtual = 47981 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13177 ; free virtual = 47927 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13161 ; free virtual = 47911 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13088 ; free virtual = 47838 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13083 ; free virtual = 47833 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13080 ; free virtual = 47831 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13080 ; free virtual = 47831 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13080 ; free virtual = 47830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13080 ; free virtual = 47830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ --------------------------------------------------------------------------------- Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 13080 ; free virtual = 47830 Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13080 ; free virtual = 47830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13078 ; free virtual = 47828 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13078 ; free virtual = 47829 INFO: [Project 1-571] Translating synthesized netlist Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 13060 ; free virtual = 47810 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 13042 ; free virtual = 47793 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13030 ; free virtual = 47781 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13028 ; free virtual = 47778 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12998 ; free virtual = 47748 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12983 ; free virtual = 47733 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12974 ; free virtual = 47725 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12975 ; free virtual = 47725 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12973 ; free virtual = 47724 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12970 ; free virtual = 47720 --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12970 ; free virtual = 47720 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 12971 ; free virtual = 47721 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12969 ; free virtual = 47720 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12951 ; free virtual = 47701 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12949 ; free virtual = 47700 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12948 ; free virtual = 47698 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12947 ; free virtual = 47697 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12946 ; free virtual = 47696 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12943 ; free virtual = 47693 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 12944 ; free virtual = 47694 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 12890 ; free virtual = 47640 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Loading route data... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Processing options... Creating bitmap... INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.949 ; gain = 0.000 ; free physical = 12737 ; free virtual = 47487 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.69 . Memory (MB): peak = 1549.949 ; gain = 0.000 ; free physical = 12711 ; free virtual = 47461 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12308 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.680 ; gain = 211.238 ; free physical = 12512 ; free virtual = 47263 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12344 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.680 ; gain = 211.238 ; free physical = 12503 ; free virtual = 47253 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12499 ; free virtual = 47249 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 12513 ; free virtual = 47263 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 12463 ; free virtual = 47214 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 12470 ; free virtual = 47220 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12469 ; free virtual = 47219 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12469 ; free virtual = 47219 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12469 ; free virtual = 47219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12468 ; free virtual = 47219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12468 ; free virtual = 47219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12468 ; free virtual = 47219 Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 12468 ; free virtual = 47219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12468 ; free virtual = 47219 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.656 ; gain = 219.215 ; free physical = 12469 ; free virtual = 47219 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12469 ; free virtual = 47220 INFO: [Project 1-571] Translating synthesized netlist Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 12448 ; free virtual = 47198 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 12321 ; free virtual = 47071 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 12312 ; free virtual = 47062 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 12164 ; free virtual = 46915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 12162 ; free virtual = 46913 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 12162 ; free virtual = 46913 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 12126 ; free virtual = 46877 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1405.672 ; gain = 322.789 ; free physical = 11906 ; free virtual = 46656 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 11873 ; free virtual = 46624 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.703 ; gain = 0.000 ; free physical = 11855 ; free virtual = 46610 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1470.703 ; gain = 0.000 ; free physical = 11866 ; free virtual = 46621 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:923] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 12077 ; free virtual = 46832 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 12069 ; free virtual = 46825 ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } --------------------------------------------------------------------------------- ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 12069 ; free virtual = 46824 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 12034 ; free virtual = 46789 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 11981 ; free virtual = 46736 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12475 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12479 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:475] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:16] INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:13:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:40 . Memory (MB): peak = 2608.441 ; gain = 389.160 ; free physical = 11760 ; free virtual = 46515 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:13:32 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 11871 ; free virtual = 46625 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 11959 ; free virtual = 46714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 11965 ; free virtual = 46720 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 12835 ; free virtual = 47589 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.949 ; gain = 115.504 ; free physical = 12932 ; free virtual = 47687 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- DONE Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 12905 ; free virtual = 47660 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12890 ; free virtual = 47645 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12769 ; free virtual = 47524 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12767 ; free virtual = 47522 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12765 ; free virtual = 47521 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12764 ; free virtual = 47520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12764 ; free virtual = 47520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12761 ; free virtual = 47516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12760 ; free virtual = 47516 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 12758 ; free virtual = 47513 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 12759 ; free virtual = 47514 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Project 1-570] Preparing netlist for logic optimization 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 12533 ; free virtual = 47294 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 12290 ; free virtual = 47051 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 12235 ; free virtual = 46996 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 12231 ; free virtual = 46992 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 12247 ; free virtual = 47008 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11862 ; free virtual = 46623 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11854 ; free virtual = 46615 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11850 ; free virtual = 46611 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11849 ; free virtual = 46610 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11846 ; free virtual = 46607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11846 ; free virtual = 46607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11845 ; free virtual = 46606 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1556.859 ; gain = 0.000 ; free physical = 11846 ; free virtual = 46607 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11842 ; free virtual = 46603 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 11841 ; free virtual = 46602 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.64 . Memory (MB): peak = 1556.859 ; gain = 0.000 ; free physical = 11785 ; free virtual = 46546 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 11771 ; free virtual = 46532 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 11761 ; free virtual = 46522 Phase 1.3 Build Placer Netlist Model Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2128.965 ; gain = 29.758 ; free physical = 11572 ; free virtual = 46333 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 11539 ; free virtual = 46300 Phase 1.3 Build Placer Netlist Model Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 11550 ; free virtual = 46311 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.953 ; gain = 36.746 ; free physical = 11486 ; free virtual = 46247 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.953 ; gain = 36.746 ; free physical = 11485 ; free virtual = 46246 Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 11492 ; free virtual = 46253 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 11481 ; free virtual = 46242 INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 11478 ; free virtual = 46239 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 11476 ; free virtual = 46237 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 11478 ; free virtual = 46239 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 11477 ; free virtual = 46238 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11476 ; free virtual = 46237 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11440 ; free virtual = 46201 Phase 3 Initial Routing Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-570] Preparing netlist for logic optimization Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 11410 ; free virtual = 46171 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11405 ; free virtual = 46166 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11387 ; free virtual = 46148 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11386 ; free virtual = 46147 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11386 ; free virtual = 46147 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11385 ; free virtual = 46146 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11384 ; free virtual = 46145 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11344 ; free virtual = 46105 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11343 ; free virtual = 46104 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11344 ; free virtual = 46105 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.008 ; gain = 56.801 ; free physical = 11380 ; free virtual = 46141 Routing Is Done. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:46 . Memory (MB): peak = 2194.797 ; gain = 95.590 ; free physical = 11381 ; free virtual = 46142 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 11378 ; free virtual = 46139 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 11395 ; free virtual = 46157 Phase 1.3 Build Placer Netlist Model 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.719 ; gain = 333.828 ; free physical = 11396 ; free virtual = 46157 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Writing placer database... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 11386 ; free virtual = 46148 Phase 1.4 Constrain Clocks/Macros Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 11383 ; free virtual = 46145 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 11383 ; free virtual = 46145 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 11379 ; free virtual = 46141 Phase 2 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11375 ; free virtual = 46137 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 11370 ; free virtual = 46133 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] Ending Placer Task | Checksum: cd729a62 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 11371 ; free virtual = 46134 WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 11371 ; free virtual = 46133 WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 11404 ; free virtual = 46169 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 11374 ; free virtual = 46139 Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer --------------------------------------------------------------------------------- Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 11375 ; free virtual = 46140 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 11371 ; free virtual = 46137 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11406 ; free virtual = 46175 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11381 ; free virtual = 46151 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11380 ; free virtual = 46149 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11374 ; free virtual = 46144 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Starting Placer Task No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.750 ; gain = 0.000 ; free physical = 11371 ; free virtual = 46141 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1482.750 ; gain = 0.000 ; free physical = 11362 ; free virtual = 46133 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11341 ; free virtual = 46113 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11335 ; free virtual = 46107 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11322 ; free virtual = 46094 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11321 ; free virtual = 46093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11323 ; free virtual = 46095 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11321 ; free virtual = 46093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11318 ; free virtual = 46090 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 11314 ; free virtual = 46087 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 11312 ; free virtual = 46084 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 11263 ; free virtual = 46037 Phase 1.4 Constrain Clocks/Macros Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 11213 ; free virtual = 45989 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 11183 ; free virtual = 45960 Phase 2 Global Placement INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 11106 ; free virtual = 45889 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Writing XDEF routing. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.797 ; gain = 0.000 ; free physical = 11100 ; free virtual = 45885 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 11008 ; free virtual = 45771 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e39310c0 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 10999 ; free virtual = 45762 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.191 ; gain = 0.000 ; free physical = 10666 ; free virtual = 45428 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.234 ; gain = 515.531 ; free physical = 10687 ; free virtual = 45450 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.234 ; gain = 515.531 ; free physical = 10680 ; free virtual = 45443 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.234 ; gain = 515.531 ; free physical = 10654 ; free virtual = 45417 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10636 ; free virtual = 45399 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.234 ; gain = 515.531 ; free physical = 10634 ; free virtual = 45397 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.234 ; gain = 515.531 ; free physical = 10621 ; free virtual = 45384 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.234 ; gain = 515.531 ; free physical = 10609 ; free virtual = 45372 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.234 ; gain = 580.562 ; free physical = 10608 ; free virtual = 45371 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10566 ; free virtual = 45329 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10560 ; free virtual = 45323 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10543 ; free virtual = 45305 Phase 3.4 Pipeline Register Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10526 ; free virtual = 45289 Phase 3.5 Small Shape Detail Placement 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 10561 ; free virtual = 45324 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Starting Routing Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1303.691 ; gain = 208.242 ; free physical = 10342 ; free virtual = 45105 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1303.691 ; gain = 208.242 ; free physical = 10355 ; free virtual = 45117 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 10353 ; free virtual = 45116 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10352 ; free virtual = 45115 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1a69706bf Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 10352 ; free virtual = 45114 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10350 ; free virtual = 45113 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10308 ; free virtual = 45071 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10273 ; free virtual = 45036 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10238 ; free virtual = 45001 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 10207 ; free virtual = 44970 --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10212 ; free virtual = 44975 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 10215 ; free virtual = 44978 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10217 ; free virtual = 44979 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10220 ; free virtual = 44983 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10229 ; free virtual = 44992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10228 ; free virtual = 44991 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10228 ; free virtual = 44991 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10228 ; free virtual = 44991 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10227 ; free virtual = 44990 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10227 ; free virtual = 44990 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10227 ; free virtual = 44990 Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10227 ; free virtual = 44990 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.676 ; gain = 216.219 ; free physical = 10229 ; free virtual = 44992 INFO: [Project 1-571] Translating synthesized netlist Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10178 ; free virtual = 44941 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10155 ; free virtual = 44918 Loading data files... Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10155 ; free virtual = 44917 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10170 ; free virtual = 44933 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 631.953 ; free physical = 10170 ; free virtual = 44933 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10083 ; free virtual = 44846 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10081 ; free virtual = 44844 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10078 ; free virtual = 44841 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10078 ; free virtual = 44841 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10079 ; free virtual = 44842 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10078 ; free virtual = 44841 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10078 ; free virtual = 44841 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10074 ; free virtual = 44837 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 10074 ; free virtual = 44837 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 9630 ; free virtual = 44393 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13604 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 9277 ; free virtual = 44040 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 9277 ; free virtual = 44040 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 9267 ; free virtual = 44030 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 9234 ; free virtual = 43997 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 9192 ; free virtual = 43955 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 9184 ; free virtual = 43947 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 9065 ; free virtual = 43828 Phase 1.3 Build Placer Netlist Model Loading site data... INFO: [Timing 38-35] Done setting XDC timing constraints. Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.238 ; gain = 0.000 ; free physical = 8596 ; free virtual = 43359 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 8564 ; free virtual = 43327 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 8560 ; free virtual = 43323 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 8558 ; free virtual = 43321 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 8554 ; free virtual = 43317 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 8550 ; free virtual = 43313 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 8550 ; free virtual = 43313 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.281 ; gain = 577.562 ; free physical = 8549 ; free virtual = 43312 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 8286 ; free virtual = 43050 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 190af02d6 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8227 ; free virtual = 42990 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2280168bc Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8225 ; free virtual = 42988 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2280168bc Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8225 ; free virtual = 42988 Phase 1 Placer Initialization | Checksum: 2280168bc Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8221 ; free virtual = 42984 Phase 2 Global Placement Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 8202 ; free virtual = 42965 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 8196 ; free virtual = 42959 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 8182 ; free virtual = 42945 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 8157 ; free virtual = 42920 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 8149 ; free virtual = 42913 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 8147 ; free virtual = 42910 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 8147 ; free virtual = 42910 --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Global Placement | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8158 ; free virtual = 42926 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8137 ; free virtual = 42904 Phase 3.2 Commit Most Macros & LUTRAMs report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b3a364ee Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8144 ; free virtual = 42911 Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d7e42b9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8070 ; free virtual = 42837 Phase 3.4 Pipeline Register Optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] Phase 3.4 Pipeline Register Optimization | Checksum: 15732a31e Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8063 ; free virtual = 42830 Phase 3.5 Small Shape Detail Placement Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.5 Small Shape Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8004 ; free virtual = 42771 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8004 ; free virtual = 42771 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8004 ; free virtual = 42771 Phase 3 Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8003 ; free virtual = 42770 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8000 ; free virtual = 42768 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 8000 ; free virtual = 42768 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8000 ; free virtual = 42768 Phase 4.3 Placer Reporting Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 4.3 Placer Reporting | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8000 ; free virtual = 42767 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7999 ; free virtual = 42766 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7998 ; free virtual = 42765 Ending Placer Task | Checksum: 181b67064 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8010 ; free virtual = 42778 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 8010 ; free virtual = 42778 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 151febe35 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7970 ; free virtual = 42737 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7970 ; free virtual = 42737 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7968 ; free virtual = 42736 Phase 1 Placer Initialization | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7967 ; free virtual = 42735 Phase 2 Global Placement WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9d16c75a ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:14:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.902 ; gain = 338.105 ; free physical = 7874 ; free virtual = 42641 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:14:17 2019... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 Phase 2 Global Placement | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8918 ; free virtual = 43686 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8915 ; free virtual = 43683 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 262698c70 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8910 ; free virtual = 43679 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23c446a3b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8897 ; free virtual = 43665 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 205f8caa0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8894 ; free virtual = 43662 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8813 ; free virtual = 43581 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8823 ; free virtual = 43592 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8815 ; free virtual = 43583 Phase 3 Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8813 ; free virtual = 43581 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8831 ; free virtual = 43599 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8836 ; free virtual = 43604 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8836 ; free virtual = 43604 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8834 ; free virtual = 43602 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8831 ; free virtual = 43600 Ending Placer Task | Checksum: 1a3769583 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8842 ; free virtual = 43611 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 8844 ; free virtual = 43612 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 8582 ; free virtual = 43350 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: bed6ec79 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 8447 ; free virtual = 43216 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 8446 ; free virtual = 43214 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 8446 ; free virtual = 43214 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 8446 ; free virtual = 43214 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 8446 ; free virtual = 43214 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 8443 ; free virtual = 43211 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 8441 ; free virtual = 43209 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 8058 ; free virtual = 42827 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 8021 ; free virtual = 42790 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 8009 ; free virtual = 42777 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 8001 ; free virtual = 42769 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 7982 ; free virtual = 42751 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 7952 ; free virtual = 42720 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 7949 ; free virtual = 42718 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 7949 ; free virtual = 42717 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 7989 ; free virtual = 42759 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.172 ; gain = 44.668 ; free physical = 8013 ; free virtual = 42803 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 7962 ; free virtual = 42751 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 7961 ; free virtual = 42751 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.176 ; gain = 42.668 ; free physical = 7933 ; free virtual = 42723 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 7888 ; free virtual = 42677 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 7887 ; free virtual = 42676 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2083.465 ; gain = 59.961 ; free physical = 7821 ; free virtual = 42610 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 7821 ; free virtual = 42591 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 7825 ; free virtual = 42595 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7823 ; free virtual = 42592 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7819 ; free virtual = 42589 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7818 ; free virtual = 42588 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7821 ; free virtual = 42591 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7821 ; free virtual = 42591 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7817 ; free virtual = 42587 Phase 7 Route finalize Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 7813 ; free virtual = 42583 Phase 3 Initial Routing Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7806 ; free virtual = 42576 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 7805 ; free virtual = 42575 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 7794 ; free virtual = 42564 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 7829 ; free virtual = 42599 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2127.254 ; gain = 135.766 ; free physical = 7829 ; free virtual = 42598 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 7814 ; free virtual = 42584 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 7811 ; free virtual = 42581 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 7811 ; free virtual = 42581 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 7811 ; free virtual = 42580 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 7810 ; free virtual = 42580 Writing placer database... Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 7809 ; free virtual = 42579 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.594 ; gain = 61.086 ; free physical = 7828 ; free virtual = 42599 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 7826 ; free virtual = 42597 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.594 ; gain = 64.086 ; free physical = 7818 ; free virtual = 42589 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.594 ; gain = 64.086 ; free physical = 7856 ; free virtual = 42627 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2126.383 ; gain = 134.891 ; free physical = 7855 ; free virtual = 42626 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 7845 ; free virtual = 42618 Writing placer database... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2126.383 ; gain = 0.000 ; free physical = 7805 ; free virtual = 42579 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 1335.066 ; gain = 239.152 ; free physical = 7541 ; free virtual = 42312 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.918 ; gain = 44.668 ; free physical = 7561 ; free virtual = 42333 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.906 ; gain = 50.656 ; free physical = 7516 ; free virtual = 42287 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.906 ; gain = 50.656 ; free physical = 7514 ; free virtual = 42286 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2079.961 ; gain = 61.711 ; free physical = 7359 ; free virtual = 42130 Phase 3 Initial Routing INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.961 ; gain = 64.711 ; free physical = 7302 ; free virtual = 42074 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.961 ; gain = 64.711 ; free physical = 7299 ; free virtual = 42070 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.961 ; gain = 64.711 ; free physical = 7299 ; free virtual = 42070 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.961 ; gain = 64.711 ; free physical = 7300 ; free virtual = 42072 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.961 ; gain = 64.711 ; free physical = 7303 ; free virtual = 42074 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.961 ; gain = 64.711 ; free physical = 7310 ; free virtual = 42081 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.961 ; gain = 64.711 ; free physical = 7282 ; free virtual = 42053 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.961 ; gain = 66.711 ; free physical = 7281 ; free virtual = 42052 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.961 ; gain = 66.711 ; free physical = 7292 ; free virtual = 42063 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.961 ; gain = 66.711 ; free physical = 7334 ; free virtual = 42105 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2123.750 ; gain = 137.516 ; free physical = 7336 ; free virtual = 42107 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing placer database... Writing XDEF routing. Loading data files... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2123.750 ; gain = 0.000 ; free physical = 7282 ; free virtual = 42055 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1339.098 ; gain = 243.184 ; free physical = 7145 ; free virtual = 41916 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1339.098 ; gain = 243.184 ; free physical = 7063 ; free virtual = 41835 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6936 ; free virtual = 41708 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15438 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6833 ; free virtual = 41605 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6848 ; free virtual = 41620 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6816 ; free virtual = 41587 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6809 ; free virtual = 41581 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6800 ; free virtual = 41572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6800 ; free virtual = 41572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6797 ; free virtual = 41569 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 6791 ; free virtual = 41563 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 6791 ; free virtual = 41563 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2129.426 ; gain = 30.227 ; free physical = 6787 ; free virtual = 41559 INFO: [Project 1-571] Translating synthesized netlist Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2135.414 ; gain = 36.215 ; free physical = 6740 ; free virtual = 41512 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2135.414 ; gain = 36.215 ; free physical = 6740 ; free virtual = 41512 Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6700 ; free virtual = 41472 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6672 ; free virtual = 41444 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6671 ; free virtual = 41443 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6671 ; free virtual = 41443 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6671 ; free virtual = 41443 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6670 ; free virtual = 41442 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6670 ; free virtual = 41442 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6687 ; free virtual = 41459 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6686 ; free virtual = 41457 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6685 ; free virtual = 41457 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 6720 ; free virtual = 41491 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:53 . Memory (MB): peak = 2193.258 ; gain = 94.059 ; free physical = 6719 ; free virtual = 41491 Writing placer database... INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Loading route data... Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.258 ; gain = 0.000 ; free physical = 6338 ; free virtual = 41133 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Creating bitstream... INFO: [Project 1-570] Preparing netlist for logic optimization Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 6252 ; free virtual = 41025 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.965 ; gain = 41.668 ; free physical = 6209 ; free virtual = 40983 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.953 ; gain = 48.656 ; free physical = 6170 ; free virtual = 40943 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.953 ; gain = 48.656 ; free physical = 6170 ; free virtual = 40943 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] Writing bitstream ./design.bit... INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.258 ; gain = 60.961 ; free physical = 6074 ; free virtual = 40851 Phase 3 Initial Routing Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.258 ; gain = 63.961 ; free physical = 6327 ; free virtual = 41106 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.258 ; gain = 63.961 ; free physical = 6313 ; free virtual = 41094 Phase 4 Rip-up And Reroute | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.258 ; gain = 63.961 ; free physical = 6318 ; free virtual = 41099 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.258 ; gain = 63.961 ; free physical = 6319 ; free virtual = 41100 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.258 ; gain = 63.961 ; free physical = 6321 ; free virtual = 41102 Phase 6 Post Hold Fix | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.258 ; gain = 63.961 ; free physical = 6322 ; free virtual = 41103 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.258 ; gain = 63.961 ; free physical = 6374 ; free virtual = 41155 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2092.258 ; gain = 65.961 ; free physical = 6375 ; free virtual = 41157 Loading route data... Phase 9 Depositing Routes Processing options... Creating bitmap... Phase 9 Depositing Routes | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2092.258 ; gain = 65.961 ; free physical = 6533 ; free virtual = 41315 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2092.258 ; gain = 65.961 ; free physical = 6584 ; free virtual = 41365 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2131.047 ; gain = 136.766 ; free physical = 6581 ; free virtual = 41363 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2131.047 ; gain = 0.000 ; free physical = 6592 ; free virtual = 41376 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:16] INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2463.430 ; gain = 336.176 ; free physical = 6523 ; free virtual = 41305 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:00 2019... Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2470.488 ; gain = 344.105 ; free physical = 7250 ; free virtual = 42032 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:00 2019... WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:7] Bitstream size: 4243411 bytes INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 Phase 1 Build RT Design | Checksum: 1a631b8be Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.074 ; gain = 50.668 ; free physical = 7642 ; free virtual = 42426 Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 8489 ; free virtual = 43272 --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1a631b8be Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8440 ; free virtual = 43229 Phase 2.2 Pre Route Cleanup touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 Phase 2.2 Pre Route Cleanup | Checksum: 1a631b8be Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8444 ; free virtual = 43233 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 8398 ; free virtual = 43181 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 8398 ; free virtual = 43181 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: 137afd744 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8355 ; free virtual = 43138 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 137afd744 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8302 ; free virtual = 43085 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 137afd744 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8299 ; free virtual = 43082 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8369 ; free virtual = 43152 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11278bc6b Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8380 ; free virtual = 43163 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8301 ; free virtual = 43084 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8304 ; free virtual = 43087 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8300 ; free virtual = 43083 Phase 4 Rip-up And Reroute | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8300 ; free virtual = 43083 Phase 5 Delay and Skew Optimization Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8298 ; free virtual = 43081 Phase 5 Delay and Skew Optimization | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8298 ; free virtual = 43081 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 4 Rip-up And Reroute | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8297 ; free virtual = 43081 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8297 ; free virtual = 43080 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8297 ; free virtual = 43080 Phase 6 Post Hold Fix | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8297 ; free virtual = 43080 Phase 6.1 Hold Fix Iter | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8293 ; free virtual = 43076 Phase 6 Post Hold Fix | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8284 ; free virtual = 43067 Phase 7 Route finalize Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8209 ; free virtual = 42992 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8207 ; free virtual = 42990 Phase 9 Depositing Routes Phase 7 Route finalize | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8206 ; free virtual = 42990 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8217 ; free virtual = 43000 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8226 ; free virtual = 43009 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8263 ; free virtual = 43046 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2140.016 ; gain = 47.473 ; free physical = 8263 ; free virtual = 43046 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 8271 ; free virtual = 43057 Phase 9 Depositing Routes | Checksum: 18b270a8f Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8267 ; free virtual = 43053 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2179.367 ; gain = 94.961 ; free physical = 8308 ; free virtual = 43094 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:53 . Memory (MB): peak = 2218.156 ; gain = 165.766 ; free physical = 8308 ; free virtual = 43094 Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing placer database... Loading data files... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 8222 ; free virtual = 43013 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.156 ; gain = 0.000 ; free physical = 8035 ; free virtual = 42847 Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8048 ; free virtual = 42865 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8071 ; free virtual = 42888 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8074 ; free virtual = 42891 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: eb842b41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8109 ; free virtual = 42900 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8207 ; free virtual = 42997 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8203 ; free virtual = 42993 Phase 4 Rip-up And Reroute | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8203 ; free virtual = 42993 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8203 ; free virtual = 42994 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8206 ; free virtual = 42997 Phase 6 Post Hold Fix | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8208 ; free virtual = 42999 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8210 ; free virtual = 43001 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8208 ; free virtual = 42999 Phase 9 Depositing Routes Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8194 ; free virtual = 42985 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 8229 ; free virtual = 43020 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2140.016 ; gain = 47.473 ; free physical = 8227 ; free virtual = 43018 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Loading data files... Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 8152 ; free virtual = 42945 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2461.855 ; gain = 338.105 ; free physical = 7993 ; free virtual = 42784 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:12 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.566 ; gain = 248.945 ; free physical = 8843 ; free virtual = 43635 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 154656e26 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2056.938 ; gain = 92.668 ; free physical = 8846 ; free virtual = 43638 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 154656e26 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2061.926 ; gain = 97.656 ; free physical = 8820 ; free virtual = 43612 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 154656e26 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2061.926 ; gain = 97.656 ; free physical = 8823 ; free virtual = 43615 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:15 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 8840 ; free virtual = 43632 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.566 ; gain = 248.945 ; free physical = 8836 ; free virtual = 43628 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8826 ; free virtual = 43618 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8820 ; free virtual = 43612 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8809 ; free virtual = 43601 Phase 4 Rip-up And Reroute | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8809 ; free virtual = 43601 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8807 ; free virtual = 43599 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8805 ; free virtual = 43597 Phase 6 Post Hold Fix | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8804 ; free virtual = 43596 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8779 ; free virtual = 43571 Phase 7 Route finalize --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 790be677 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8779 ; free virtual = 43571 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 790be677 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 8778 ; free virtual = 43570 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 790be677 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 8775 ; free virtual = 43567 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 8805 ; free virtual = 43597 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2110.770 ; gain = 178.516 ; free physical = 8804 ; free virtual = 43596 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 8768 ; free virtual = 43560 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing placer database... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 8759 ; free virtual = 43551 Phase 2.2 Pre Route Cleanup Writing XDEF routing. Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 8759 ; free virtual = 43551 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 8776 ; free virtual = 43569 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.465 ; gain = 59.961 ; free physical = 8648 ; free virtual = 43440 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8602 ; free virtual = 43394 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8619 ; free virtual = 43411 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 8590 ; free virtual = 43383 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8582 ; free virtual = 43374 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8618 ; free virtual = 43411 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8611 ; free virtual = 43403 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 8611 ; free virtual = 43404 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 8609 ; free virtual = 43401 --------------------------------------------------------------------------------- Phase 5 Delay and Skew Optimization Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8609 ; free virtual = 43401 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 8606 ; free virtual = 43399 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8605 ; free virtual = 43397 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 8612 ; free virtual = 43404 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 8603 ; free virtual = 43395 Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8604 ; free virtual = 43396 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.598 ; gain = 269.969 ; free physical = 8610 ; free virtual = 43402 Running DRC as a precondition to command write_bitstream Phase 7 Route finalize Starting Placer Task Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-571] Translating synthesized netlist Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 8541 ; free virtual = 43334 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 8541 ; free virtual = 43333 Phase 9 Depositing Routes Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 8599 ; free virtual = 43391 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 8636 ; free virtual = 43428 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2127.254 ; gain = 135.766 ; free physical = 8634 ; free virtual = 43427 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1554.855 ; gain = 0.000 ; free physical = 8633 ; free virtual = 43426 Writing placer database... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.59 . Memory (MB): peak = 1554.855 ; gain = 0.000 ; free physical = 8569 ; free virtual = 43361 Writing XDEF routing. Loading site data... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 8467 ; free virtual = 43262 Loading data files... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:23 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2531.363 ; gain = 338.105 ; free physical = 8088 ; free virtual = 42885 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:23 2019... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 Loading data files... Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15963 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15977 Writing bitstream ./design.bit... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Creating bitstream... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.262 ; gain = 384.367 ; free physical = 8659 ; free virtual = 43460 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1546.965 ; gain = 0.000 ; free physical = 8615 ; free virtual = 43416 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.50 . Memory (MB): peak = 1546.965 ; gain = 0.000 ; free physical = 8598 ; free virtual = 43399 Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2470.152 ; gain = 339.105 ; free physical = 8668 ; free virtual = 43473 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:33 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading route data... Processing options... Creating bitmap... touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:36 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2475.121 ; gain = 335.105 ; free physical = 9499 ; free virtual = 44306 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:36 2019... Bitstream size: 4243411 bytes Creating bitstream... Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 10063 ; free virtual = 44870 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 9995 ; free virtual = 44803 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16213 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 9948 ; free virtual = 44755 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 9978 ; free virtual = 44790 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 10082 ; free virtual = 44899 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10085 ; free virtual = 44901 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 10101 ; free virtual = 44917 --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 10151 ; free virtual = 44968 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10493 ; free virtual = 45310 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10521 ; free virtual = 45338 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10532 ; free virtual = 45349 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 10476 ; free virtual = 45293 Phase 1.3 Build Placer Netlist Model Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 2453.875 ; gain = 343.105 ; free physical = 10629 ; free virtual = 45450 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:46 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2475.121 ; gain = 335.105 ; free physical = 10650 ; free virtual = 45470 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:47 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 10848 ; free virtual = 45668 Phase 1.4 Constrain Clocks/Macros Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 12575 ; free virtual = 47396 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 DONE Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 12570 ; free virtual = 47391 Phase 2 Final Placement Cleanup touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 12525 ; free virtual = 47346 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 497.531 ; free physical = 12530 ; free virtual = 47351 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 12519 ; free virtual = 47340 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:48 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2471.359 ; gain = 344.105 ; free physical = 12507 ; free virtual = 47328 INFO: Launching helper process for spawning children vivado processes INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:48 2019... INFO: Helper process launched with PID 16364 Writing bitstream ./design.bit... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 13683 ; free virtual = 48509 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 13694 ; free virtual = 48519 --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 13667 ; free virtual = 48493 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13651 ; free virtual = 48477 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 13624 ; free virtual = 48449 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 13613 ; free virtual = 48439 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13549 ; free virtual = 48375 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13500 ; free virtual = 48326 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13487 ; free virtual = 48313 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13487 ; free virtual = 48313 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13490 ; free virtual = 48316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13488 ; free virtual = 48315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13485 ; free virtual = 48313 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13481 ; free virtual = 48311 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13475 ; free virtual = 48305 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 13474 ; free virtual = 48305 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 13438 ; free virtual = 48265 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13426 ; free virtual = 48257 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13476 ; free virtual = 48305 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 13475 ; free virtual = 48302 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 13470 ; free virtual = 48296 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13465 ; free virtual = 48292 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13467 ; free virtual = 48293 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13465 ; free virtual = 48292 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13464 ; free virtual = 48290 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13492 ; free virtual = 48319 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13487 ; free virtual = 48313 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 13487 ; free virtual = 48314 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 13486 ; free virtual = 48313 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:15:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:43 . Memory (MB): peak = 2606.316 ; gain = 388.160 ; free physical = 13444 ; free virtual = 48271 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:15:52 2019... INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Project 1-570] Preparing netlist for logic optimization touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.453 ; gain = 0.000 ; free physical = 14238 ; free virtual = 49064 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.168 ; gain = 456.203 ; free physical = 14097 ; free virtual = 48924 Phase 1.3 Build Placer Netlist Model ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 13901 ; free virtual = 48727 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 13905 ; free virtual = 48731 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16662 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 13788 ; free virtual = 48615 --------------------------------------------------------------------------------- Starting Placer Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 13784 ; free virtual = 48610 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 13777 ; free virtual = 48604 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 13762 ; free virtual = 48588 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 13754 ; free virtual = 48581 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.168 ; gain = 456.203 ; free physical = 13712 ; free virtual = 48539 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.168 ; gain = 456.203 ; free physical = 13693 ; free virtual = 48519 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.168 ; gain = 456.203 ; free physical = 13628 ; free virtual = 48454 Phase 2 Global Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] No constraint files found.INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer --------------------------------------------------------------------------------- Parameter DREG bound to: 1 - type: integer Start Cross Boundary and Area Optimization Parameter INMODEREG bound to: 1 - type: integer --------------------------------------------------------------------------------- Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 13571 ; free virtual = 48398 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] --------------------------------------------------------------------------------- Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Launching helper process for spawning children vivado processes INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] INFO: Helper process launched with PID 16918 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 13457 ; free virtual = 48284 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13511 ; free virtual = 48338 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 13596 ; free virtual = 48423 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 13576 ; free virtual = 48403 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 13576 ; free virtual = 48403 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 13511 ; free virtual = 48338 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13348 ; free virtual = 48175 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13343 ; free virtual = 48171 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13341 ; free virtual = 48168 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13341 ; free virtual = 48168 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13340 ; free virtual = 48167 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13340 ; free virtual = 48167 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13337 ; free virtual = 48164 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 13336 ; free virtual = 48163 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13337 ; free virtual = 48164 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 13277 ; free virtual = 48104 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 13258 ; free virtual = 48085 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 13223 ; free virtual = 48050 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 13216 ; free virtual = 48043 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 13195 ; free virtual = 48022 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 12954 ; free virtual = 47781 Phase 3.6 Re-assign LUT pins ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 13063 ; free virtual = 47890 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 12991 ; free virtual = 47818 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 12944 ; free virtual = 47771 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 13041 ; free virtual = 47868 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 13029 ; free virtual = 47856 Phase 4.2 Post Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 13004 ; free virtual = 47831 Phase 4.3 Placer Reporting INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 12967 ; free virtual = 47794 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 12963 ; free virtual = 47793 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 12941 ; free virtual = 47768 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17468 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 12931 ; free virtual = 47759 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 12955 ; free virtual = 47782 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 12942 ; free virtual = 47769 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.211 ; gain = 544.246 ; free physical = 12929 ; free virtual = 47756 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.211 ; gain = 623.949 ; free physical = 12936 ; free virtual = 47763 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12922 ; free virtual = 47749 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 12922 ; free virtual = 47749 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 12921 ; free virtual = 47748 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17513 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 12845 ; free virtual = 47672 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12769 ; free virtual = 47596 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12766 ; free virtual = 47593 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12781 ; free virtual = 47608 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12781 ; free virtual = 47608 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12780 ; free virtual = 47607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12775 ; free virtual = 47602 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12774 ; free virtual = 47602 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 12772 ; free virtual = 47599 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 12773 ; free virtual = 47601 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17551 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 12723 ; free virtual = 47550 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 12708 ; free virtual = 47536 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Parameter DOA_REG bound to: 0 - type: integer Start Loading Part and Timing Information --------------------------------------------------------------------------------- Parameter DOB_REG bound to: 0 - type: integer Loading part: xc7z020clg400-1 Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 12708 ; free virtual = 47536 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 12675 ; free virtual = 47503 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 12678 ; free virtual = 47505 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 12662 ; free virtual = 47490 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 12662 ; free virtual = 47490 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 12653 ; free virtual = 47481 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17601 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 12166 ; free virtual = 46994 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.992 ; free physical = 11622 ; free virtual = 46450 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 11500 ; free virtual = 46328 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 11484 ; free virtual = 46313 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.203 ; gain = 0.000 ; free physical = 11445 ; free virtual = 46273 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 11389 ; free virtual = 46218 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 11376 ; free virtual = 46204 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 11370 ; free virtual = 46198 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 11366 ; free virtual = 46194 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 11361 ; free virtual = 46189 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 11362 ; free virtual = 46190 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 580.562 ; free physical = 11362 ; free virtual = 46190 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1903.453 ; gain = 0.000 ; free physical = 11361 ; free virtual = 46189 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11375 ; free virtual = 46204 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 11342 ; free virtual = 46170 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 11335 ; free virtual = 46164 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 11327 ; free virtual = 46155 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:251] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1427] Phase 1 Placer Initialization | Checksum: eaaa372b WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1455] Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 11317 ; free virtual = 46146 Phase 2 Final Placement Cleanup WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 11307 ; free virtual = 46135 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:16] Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 11307 ; free virtual = 46136 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.496 ; gain = 584.562 ; free physical = 11307 ; free virtual = 46135 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 11301 ; free virtual = 46129 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 11315 ; free virtual = 46143 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.992 ; free physical = 11310 ; free virtual = 46138 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 11296 ; free virtual = 46125 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 11295 ; free virtual = 46124 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 11285 ; free virtual = 46114 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11269 ; free virtual = 46098 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.949 ; gain = 115.508 ; free physical = 11243 ; free virtual = 46075 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 11224 ; free virtual = 46053 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 11204 ; free virtual = 46033 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11212 ; free virtual = 46040 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11205 ; free virtual = 46034 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11183 ; free virtual = 46012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11181 ; free virtual = 46010 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11173 ; free virtual = 46002 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11172 ; free virtual = 46001 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11172 ; free virtual = 46001 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11172 ; free virtual = 46001 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11171 ; free virtual = 46000 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11170 ; free virtual = 45999 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ --------------------------------------------------------------------------------- +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11169 ; free virtual = 45998 No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Report Cell Usage: Detailed RTL Component Info : +------+---------+------+ | |Cell |Count | +------+---------+------+ --------------------------------------------------------------------------------- |1 |RAMB18E1 | 280| +------+---------+------+ Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11169 ; free virtual = 45997 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11171 ; free virtual = 46000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 11172 ; free virtual = 46001 INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:139] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 11194 ; free virtual = 46023 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 11188 ; free virtual = 46017 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 11184 ; free virtual = 46013 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11175 ; free virtual = 46004 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11174 ; free virtual = 46003 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11173 ; free virtual = 46002 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11172 ; free virtual = 46001 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11172 ; free virtual = 46001 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11172 ; free virtual = 46001 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11171 ; free virtual = 46000 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11169 ; free virtual = 45998 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 11170 ; free virtual = 45999 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.949 ; gain = 115.508 ; free physical = 11141 ; free virtual = 45970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 10905 ; free virtual = 45734 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 10147 ; free virtual = 44985 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 10165 ; free virtual = 44995 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 10141 ; free virtual = 44977 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 10140 ; free virtual = 44975 --------------------------------------------------------------------------------- 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 10139 ; free virtual = 44974 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Timing 38-35] Done setting XDC timing constraints. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1899.195 ; gain = 0.000 ; free physical = 10130 ; free virtual = 44960 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 10100 ; free virtual = 44930 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 516.531 ; free physical = 10086 ; free virtual = 44916 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 516.531 ; free physical = 10073 ; free virtual = 44903 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 516.531 ; free physical = 10071 ; free virtual = 44901 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 10078 ; free virtual = 44908 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 516.531 ; free physical = 10077 ; free virtual = 44907 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 516.531 ; free physical = 10076 ; free virtual = 44906 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 516.531 ; free physical = 10081 ; free virtual = 44910 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.238 ; gain = 581.562 ; free physical = 10080 ; free virtual = 44910 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Starting Placer Task Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1483.742 ; gain = 0.000 ; free physical = 10063 ; free virtual = 44892 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1483.742 ; gain = 0.000 ; free physical = 10050 ; free virtual = 44880 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 10049 ; free virtual = 44879 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 10038 ; free virtual = 44868 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1577c780a Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2135.070 ; gain = 50.668 ; free physical = 10004 ; free virtual = 44833 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 9988 ; free virtual = 44821 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 9987 ; free virtual = 44821 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 9956 ; free virtual = 44786 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints | Checksum: 1577c780a Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2144.059 ; gain = 59.656 ; free physical = 9948 ; free virtual = 44778 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1577c780a Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2144.059 ; gain = 59.656 ; free physical = 9949 ; free virtual = 44779 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 9945 ; free virtual = 44775 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9946 ; free virtual = 44776 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 9936 ; free virtual = 44766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9932 ; free virtual = 44762 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9931 ; free virtual = 44760 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9929 ; free virtual = 44759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9929 ; free virtual = 44759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9929 ; free virtual = 44759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9927 ; free virtual = 44756 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9926 ; free virtual = 44756 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 9927 ; free virtual = 44757 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9906 ; free virtual = 44735 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9917 ; free virtual = 44747 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9894 ; free virtual = 44724 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9872 ; free virtual = 44702 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9868 ; free virtual = 44697 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9867 ; free virtual = 44697 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9863 ; free virtual = 44693 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9862 ; free virtual = 44692 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9858 ; free virtual = 44688 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9857 ; free virtual = 44686 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9856 ; free virtual = 44686 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9851 ; free virtual = 44681 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9849 ; free virtual = 44679 INFO: [Project 1-571] Translating synthesized netlist Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9809 ; free virtual = 44639 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9806 ; free virtual = 44636 Phase 4 Rip-up And Reroute | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9806 ; free virtual = 44636 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9805 ; free virtual = 44635 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9804 ; free virtual = 44634 Phase 6 Post Hold Fix | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9804 ; free virtual = 44633 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9801 ; free virtual = 44631 --------------------------------------------------------------------------------- Phase 7 Route finalize Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9800 ; free virtual = 44630 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9799 ; free virtual = 44629 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9799 ; free virtual = 44629 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9798 ; free virtual = 44628 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9798 ; free virtual = 44628 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9798 ; free virtual = 44628 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9799 ; free virtual = 44629 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9801 ; free virtual = 44631 INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9786 ; free virtual = 44616 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9782 ; free virtual = 44612 Phase 9 Depositing Routes INFO: [Project 1-570] Preparing netlist for logic optimization Phase 9 Depositing Routes | Checksum: 17ae0cba6 Time (s): cpu = 00:00:46 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9808 ; free virtual = 44638 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:46 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.488 ; gain = 95.086 ; free physical = 9851 ; free virtual = 44681 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:46 . Memory (MB): peak = 2218.277 ; gain = 165.891 ; free physical = 9851 ; free virtual = 44681 INFO: [Project 1-570] Preparing netlist for logic optimization Writing placer database... INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 9182 ; free virtual = 44034 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.277 ; gain = 0.000 ; free physical = 9196 ; free virtual = 44056 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.930 ; gain = 342.047 ; free physical = 9207 ; free virtual = 44066 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 9205 ; free virtual = 44064 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.449 ; gain = 0.000 ; free physical = 9208 ; free virtual = 44067 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 9180 ; free virtual = 44040 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9182 ; free virtual = 44043 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2218.277 ; gain = 0.000 ; free physical = 9221 ; free virtual = 44054 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9231 ; free virtual = 44063 Phase 1.3 Build Placer Netlist Model 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.930 ; gain = 342.047 ; free physical = 9251 ; free virtual = 44084 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9247 ; free virtual = 44080 Starting Placer Task Phase 1.4 Constrain Clocks/Macros INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 9242 ; free virtual = 44074 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 9241 ; free virtual = 44074 Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9240 ; free virtual = 44072 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9231 ; free virtual = 44063 Phase 2 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9220 ; free virtual = 44053 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9221 ; free virtual = 44054 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.492 ; gain = 583.562 ; free physical = 9221 ; free virtual = 44053 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 9156 ; free virtual = 43989 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1585d46d4 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 9161 ; free virtual = 43994 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9137 ; free virtual = 43970 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 9137 ; free virtual = 43970 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9137 ; free virtual = 43970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15fdaa0f7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 9130 ; free virtual = 43963 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9130 ; free virtual = 43963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9129 ; free virtual = 43962 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9128 ; free virtual = 43961 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9125 ; free virtual = 43958 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9123 ; free virtual = 43956 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9121 ; free virtual = 43954 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 9122 ; free virtual = 43955 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 1416.719 ; gain = 333.828 ; free physical = 8419 ; free virtual = 43252 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 8194 ; free virtual = 43027 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.750 ; gain = 0.000 ; free physical = 8178 ; free virtual = 43011 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1482.750 ; gain = 0.000 ; free physical = 8176 ; free virtual = 43009 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 8082 ; free virtual = 42915 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 7985 ; free virtual = 42818 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 7966 ; free virtual = 42799 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 7925 ; free virtual = 42758 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 7932 ; free virtual = 42765 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 510.531 ; free physical = 7944 ; free virtual = 42777 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 7943 ; free virtual = 42776 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 7887 ; free virtual = 42720 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 7877 ; free virtual = 42710 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 7876 ; free virtual = 42709 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 7876 ; free virtual = 42709 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 7876 ; free virtual = 42709 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 7875 ; free virtual = 42708 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Loading data files... Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 7873 ; free virtual = 42706 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 7873 ; free virtual = 42706 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2129.441 ; gain = 38.230 ; free physical = 7778 ; free virtual = 42611 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.430 ; gain = 44.219 ; free physical = 7730 ; free virtual = 42563 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.430 ; gain = 44.219 ; free physical = 7730 ; free virtual = 42563 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7687 ; free virtual = 42520 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7680 ; free virtual = 42513 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7679 ; free virtual = 42513 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7679 ; free virtual = 42512 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7679 ; free virtual = 42512 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7679 ; free virtual = 42512 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7679 ; free virtual = 42512 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7666 ; free virtual = 42499 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7665 ; free virtual = 42498 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7666 ; free virtual = 42499 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.484 ; gain = 63.273 ; free physical = 7701 ; free virtual = 42534 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2193.273 ; gain = 102.062 ; free physical = 7701 ; free virtual = 42534 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.273 ; gain = 0.000 ; free physical = 7055 ; free virtual = 41911 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 6800 ; free virtual = 41657 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.449 ; gain = 0.000 ; free physical = 6535 ; free virtual = 41370 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.449 ; gain = 0.000 ; free physical = 6528 ; free virtual = 41362 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 6440 ; free virtual = 41274 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 6434 ; free virtual = 41268 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 6434 ; free virtual = 41268 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 6433 ; free virtual = 41267 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 6432 ; free virtual = 41266 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 6431 ; free virtual = 41265 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 6431 ; free virtual = 41265 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d38ee6f1 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6397 ; free virtual = 41231 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 26ae14cd7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6388 ; free virtual = 41223 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 26ae14cd7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6384 ; free virtual = 41218 Phase 1 Placer Initialization | Checksum: 26ae14cd7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6380 ; free virtual = 41214 Phase 2 Global Placement WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1dac8b64b Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6320 ; free virtual = 41155 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6320 ; free virtual = 41155 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6321 ; free virtual = 41156 Phase 1 Placer Initialization | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6321 ; free virtual = 41155 Phase 2 Global Placement Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2061.930 ; gain = 43.668 ; free physical = 6319 ; free virtual = 41153 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.180 ; gain = 44.668 ; free physical = 6282 ; free virtual = 41116 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.918 ; gain = 48.656 ; free physical = 6270 ; free virtual = 41104 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.918 ; gain = 48.656 ; free physical = 6270 ; free virtual = 41104 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.168 ; gain = 50.656 ; free physical = 6235 ; free virtual = 41070 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.168 ; gain = 50.656 ; free physical = 6235 ; free virtual = 41070 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Number of Nodes with overlaps = 0 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 6192 ; free virtual = 41026 Phase 3 Initial Routing Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2077.098 ; gain = 58.836 ; free physical = 6193 ; free virtual = 41028 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.098 ; gain = 60.836 ; free physical = 6196 ; free virtual = 41031 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 6196 ; free virtual = 41030 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.098 ; gain = 60.836 ; free physical = 6195 ; free virtual = 41030 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.098 ; gain = 60.836 ; free physical = 6194 ; free virtual = 41029 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.098 ; gain = 60.836 ; free physical = 6194 ; free virtual = 41029 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.098 ; gain = 60.836 ; free physical = 6194 ; free virtual = 41029 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.098 ; gain = 60.836 ; free physical = 6194 ; free virtual = 41029 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 6194 ; free virtual = 41028 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 6194 ; free virtual = 41028 Phase 5 Delay and Skew Optimization Phase 7 Route finalize Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 6193 ; free virtual = 41027 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 6190 ; free virtual = 41025 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 6189 ; free virtual = 41024 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.098 ; gain = 60.836 ; free physical = 6188 ; free virtual = 41023 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.098 ; gain = 62.836 ; free physical = 6191 ; free virtual = 41026 Phase 9 Depositing Routes Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.098 ; gain = 62.836 ; free physical = 6189 ; free virtual = 41023 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.098 ; gain = 62.836 ; free physical = 6223 ; free virtual = 41057 Routing Is Done. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 6222 ; free virtual = 41057 Phase 8 Verifying routed nets 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2119.887 ; gain = 133.641 ; free physical = 6217 ; free virtual = 41051 Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.473 ; gain = 64.961 ; free physical = 6216 ; free virtual = 41050 Phase 9 Depositing Routes Writing placer database... Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.473 ; gain = 64.961 ; free physical = 6167 ; free virtual = 41002 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.473 ; gain = 64.961 ; free physical = 6205 ; free virtual = 41039 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2127.262 ; gain = 135.766 ; free physical = 6232 ; free virtual = 41066 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2119.887 ; gain = 0.000 ; free physical = 6371 ; free virtual = 41208 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 262ca559a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6390 ; free virtual = 41226 Writing XDEF routing. Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 262ca559a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6377 ; free virtual = 41215 Phase 3.2 Commit Most Macros & LUTRAMs Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 23e660b1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6365 ; free virtual = 41203 Write XDEF Complete: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:01 . Memory (MB): peak = 2127.262 ; gain = 0.000 ; free physical = 6357 ; free virtual = 41195 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21840e8ea Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6350 ; free virtual = 41189 Phase 3.4 Pipeline Register Optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.4 Pipeline Register Optimization | Checksum: 1e1f5494f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6349 ; free virtual = 41185 Phase 3.5 Small Shape Detail Placement INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 26a0424f4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6382 ; free virtual = 41217 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26a0424f4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6407 ; free virtual = 41242 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22a14ef89 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6387 ; free virtual = 41222 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 203efcd54 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6361 ; free virtual = 41196 Phase 3.4 Pipeline Register Optimization Phase 3.5 Small Shape Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6354 ; free virtual = 41190 Phase 3.6 Re-assign LUT pins Phase 3.4 Pipeline Register Optimization | Checksum: 1cda42db9 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6352 ; free virtual = 41188 Phase 3.5 Small Shape Detail Placement Phase 3.6 Re-assign LUT pins | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6350 ; free virtual = 41186 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6343 ; free virtual = 41179 Phase 3 Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6335 ; free virtual = 41170 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6320 ; free virtual = 41156 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6306 ; free virtual = 41142 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6301 ; free virtual = 41136 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6289 ; free virtual = 41125 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6282 ; free virtual = 41117 Ending Placer Task | Checksum: 1cc0c8886 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 6282 ; free virtual = 41117 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2092.539 ; gain = 667.609 ; free physical = 6280 ; free virtual = 41115 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6303 ; free virtual = 41139 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6300 ; free virtual = 41136 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6298 ; free virtual = 41134 Phase 3 Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6299 ; free virtual = 41135 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6293 ; free virtual = 41129 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6287 ; free virtual = 41122 Phase 4.3 Placer Reporting Running DRC as a precondition to command write_bitstream Phase 4.3 Placer Reporting | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6310 ; free virtual = 41146 Phase 4.4 Final Placement Cleanup INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 4.4 Final Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6316 ; free virtual = 41152 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Post Placement Optimization and Clean-Up | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6313 ; free virtual = 41149 Ending Placer Task | Checksum: 1c8c94742 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 6329 ; free virtual = 41165 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 2084.535 ; gain = 659.605 ; free physical = 6329 ; free virtual = 41164 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e76cdf7c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4299e38 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.238 ; gain = 0.000 ; free physical = 5505 ; free virtual = 40340 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 5464 ; free virtual = 40299 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 5453 ; free virtual = 40289 Phase 1.4 Constrain Clocks/Macros Creating bitstream... Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 5485 ; free virtual = 40320 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 5479 ; free virtual = 40315 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 5467 ; free virtual = 40303 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 5460 ; free virtual = 40295 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:30 . Memory (MB): peak = 1994.281 ; gain = 577.562 ; free physical = 5449 ; free virtual = 40285 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2062.922 ; gain = 43.668 ; free physical = 5323 ; free virtual = 40163 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.910 ; gain = 49.656 ; free physical = 5287 ; free virtual = 40127 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.910 ; gain = 49.656 ; free physical = 5287 ; free virtual = 40126 Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2078.965 ; gain = 59.711 ; free physical = 5195 ; free virtual = 40034 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 5209 ; free virtual = 40048 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 5206 ; free virtual = 40046 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 5206 ; free virtual = 40046 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 5206 ; free virtual = 40046 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 5206 ; free virtual = 40046 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 5206 ; free virtual = 40046 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 5204 ; free virtual = 40044 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2083.965 ; gain = 64.711 ; free physical = 5204 ; free virtual = 40044 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2083.965 ; gain = 64.711 ; free physical = 5203 ; free virtual = 40043 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2083.965 ; gain = 64.711 ; free physical = 5230 ; free virtual = 40070 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2122.754 ; gain = 135.516 ; free physical = 5230 ; free virtual = 40070 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2122.754 ; gain = 0.000 ; free physical = 5217 ; free virtual = 40060 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:17:26 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:48 . Memory (MB): peak = 2607.438 ; gain = 389.160 ; free physical = 5184 ; free virtual = 40024 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:17:26 2019... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2067.176 ; gain = 44.668 ; free physical = 5947 ; free virtual = 40796 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2073.164 ; gain = 50.656 ; free physical = 5936 ; free virtual = 40785 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2073.164 ; gain = 50.656 ; free physical = 5950 ; free virtual = 40799 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2084.469 ; gain = 61.961 ; free physical = 6143 ; free virtual = 40992 Phase 3 Initial Routing Loading data files... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 6136 ; free virtual = 40985 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 6133 ; free virtual = 40982 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 6132 ; free virtual = 40981 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 6130 ; free virtual = 40979 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 6130 ; free virtual = 40979 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 6130 ; free virtual = 40979 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 6131 ; free virtual = 40980 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 6131 ; free virtual = 40980 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.469 ; gain = 66.961 ; free physical = 6143 ; free virtual = 40992 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.469 ; gain = 66.961 ; free physical = 6203 ; free virtual = 41053 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2128.258 ; gain = 137.766 ; free physical = 6205 ; free virtual = 41054 Creating bitstream... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 6188 ; free virtual = 41041 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:17:36 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2531.379 ; gain = 338.105 ; free physical = 6106 ; free virtual = 40956 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:17:36 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Writing bitstream ./design.bit... Creating bitstream... touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.930 ; gain = 41.668 ; free physical = 7416 ; free virtual = 42270 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.918 ; gain = 47.656 ; free physical = 7402 ; free virtual = 42256 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.918 ; gain = 47.656 ; free physical = 7401 ; free virtual = 42255 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.973 ; gain = 58.711 ; free physical = 7311 ; free virtual = 42166 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 7311 ; free virtual = 42165 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 7297 ; free virtual = 42152 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 7296 ; free virtual = 42151 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 7294 ; free virtual = 42149 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 7293 ; free virtual = 42148 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 7292 ; free virtual = 42147 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 7251 ; free virtual = 42106 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 7251 ; free virtual = 42106 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 7263 ; free virtual = 42118 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 7299 ; free virtual = 42154 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2120.762 ; gain = 133.516 ; free physical = 7300 ; free virtual = 42155 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2120.762 ; gain = 0.000 ; free physical = 7308 ; free virtual = 42165 Writing bitstream ./design.bit... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:17:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2462.438 ; gain = 335.176 ; free physical = 7591 ; free virtual = 42451 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:17:40 2019... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:17:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading route data... Processing options... Creating bitmap... 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2461.992 ; gain = 342.105 ; free physical = 8298 ; free virtual = 43158 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:17:43 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 Loading data files... Phase 1 Build RT Design | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 9003 ; free virtual = 43865 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2073.945 ; gain = 47.656 ; free physical = 8985 ; free virtual = 43846 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2073.945 ; gain = 47.656 ; free physical = 8983 ; free virtual = 43845 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2086.250 ; gain = 59.961 ; free physical = 8906 ; free virtual = 43768 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:55 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8858 ; free virtual = 43720 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8854 ; free virtual = 43716 Phase 4 Rip-up And Reroute | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8853 ; free virtual = 43715 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8851 ; free virtual = 43712 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8848 ; free virtual = 43709 Phase 6 Post Hold Fix | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8847 ; free virtual = 43709 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8831 ; free virtual = 43693 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 8829 ; free virtual = 43691 Phase 9 Depositing Routes Loading site data... Phase 9 Depositing Routes | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 8816 ; free virtual = 43678 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 8853 ; free virtual = 43715 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2130.039 ; gain = 135.766 ; free physical = 8853 ; free virtual = 43715 Writing placer database... Loading route data... Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2130.039 ; gain = 0.000 ; free physical = 8848 ; free virtual = 43713 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20094 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... Phase 1 Build RT Design | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2058.930 ; gain = 94.668 ; free physical = 8936 ; free virtual = 43807 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 8910 ; free virtual = 43781 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 8909 ; free virtual = 43780 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 8953 ; free virtual = 43823 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 8940 ; free virtual = 43811 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 8938 ; free virtual = 43809 Phase 4 Rip-up And Reroute | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 8938 ; free virtual = 43809 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 8938 ; free virtual = 43809 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 8937 ; free virtual = 43808 Phase 6 Post Hold Fix | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 8937 ; free virtual = 43807 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 96eb7d44 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 8920 ; free virtual = 43791 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 96eb7d44 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 8919 ; free virtual = 43789 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 96eb7d44 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 8918 ; free virtual = 43789 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 8950 ; free virtual = 43821 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:55 . Memory (MB): peak = 2112.762 ; gain = 180.516 ; free physical = 8952 ; free virtual = 43823 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:17:57 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2460.859 ; gain = 338.105 ; free physical = 8956 ; free virtual = 43826 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:17:57 2019... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2112.762 ; gain = 0.000 ; free physical = 8960 ; free virtual = 43832 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:17:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2470.363 ; gain = 342.105 ; free physical = 9790 ; free virtual = 44662 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:17:58 2019... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20243 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: ff03af09 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 10611 ; free virtual = 45483 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ff03af09 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 10561 ; free virtual = 45433 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ff03af09 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 10561 ; free virtual = 45433 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b4ae2ab4 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10544 ; free virtual = 45417 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10474 ; free virtual = 45347 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10461 ; free virtual = 45334 Phase 4 Rip-up And Reroute | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10461 ; free virtual = 45334 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10461 ; free virtual = 45334 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10464 ; free virtual = 45337 Phase 6 Post Hold Fix | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10467 ; free virtual = 45340 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 130e541f3 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10468 ; free virtual = 45341 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 130e541f3 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10463 ; free virtual = 45336 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 130e541f3 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10467 ; free virtual = 45340 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 10505 ; free virtual = 45378 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2141.012 ; gain = 56.477 ; free physical = 10507 ; free virtual = 45380 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2141.012 ; gain = 0.000 ; free physical = 10431 ; free virtual = 45306 Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 15ca2bf97 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 10412 ; free virtual = 45286 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15ca2bf97 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 10376 ; free virtual = 45250 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15ca2bf97 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 10378 ; free virtual = 45251 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: fe41f556 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10307 ; free virtual = 45180 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 10280 ; free virtual = 45153 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10275 ; free virtual = 45149 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10272 ; free virtual = 45146 Phase 4 Rip-up And Reroute | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10272 ; free virtual = 45145 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10271 ; free virtual = 45145 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10271 ; free virtual = 45145 Phase 6 Post Hold Fix | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10271 ; free virtual = 45144 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 7 Route finalize | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10269 ; free virtual = 45142 Phase 8 Verifying routed nets Verification completed successfully INFO: Launching helper process for spawning children vivado processes Phase 8 Verifying routed nets | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10264 ; free virtual = 45137 Phase 9 Depositing Routes INFO: Helper process launched with PID 20366 Phase 9 Depositing Routes | Checksum: e279f4d5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10247 ; free virtual = 45121 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.223 ; gain = 8.684 ; free physical = 10279 ; free virtual = 45152 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:56 . Memory (MB): peak = 2140.012 ; gain = 47.473 ; free physical = 10277 ; free virtual = 45151 Writing bitstream ./design.bit... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2140.012 ; gain = 0.000 ; free physical = 10172 ; free virtual = 45052 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1 Build RT Design | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.965 ; gain = 41.668 ; free physical = 10350 ; free virtual = 45228 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.953 ; gain = 47.656 ; free physical = 10325 ; free virtual = 45203 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.953 ; gain = 47.656 ; free physical = 10321 ; free virtual = 45199 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.258 ; gain = 60.961 ; free physical = 10206 ; free virtual = 45084 Phase 3 Initial Routing INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 10219 ; free virtual = 45097 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 10205 ; free virtual = 45083 Phase 4 Rip-up And Reroute | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 10204 ; free virtual = 45082 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 10201 ; free virtual = 45079 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 10200 ; free virtual = 45079 Phase 6 Post Hold Fix | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 10199 ; free virtual = 45078 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 10163 ; free virtual = 45041 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.258 ; gain = 64.961 ; free physical = 10159 ; free virtual = 45037 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.258 ; gain = 64.961 ; free physical = 10164 ; free virtual = 45042 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.258 ; gain = 64.961 ; free physical = 10200 ; free virtual = 45079 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2130.047 ; gain = 135.766 ; free physical = 10200 ; free virtual = 45079 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:18:08 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 2459.867 ; gain = 339.105 ; free physical = 10190 ; free virtual = 45068 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:18:09 2019... Loading data files... Writing placer database... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20450 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.65 . Memory (MB): peak = 2130.047 ; gain = 0.000 ; free physical = 10294 ; free virtual = 45176 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 11039 ; free virtual = 45918 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Loading route data... Processing options... Creating bitmap... Loading data files... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 10263 ; free virtual = 45143 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] Creating bitstream... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10140 ; free virtual = 45021 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10142 ; free virtual = 45026 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] Loading site data... Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 10145 ; free virtual = 45029 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 10319 ; free virtual = 45203 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:18:21 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1422] 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1505] write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 2468.145 ; gain = 338.105 ; free physical = 10319 ; free virtual = 45207 WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:18:21 2019... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:16] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 10430 ; free virtual = 45321 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20606 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 11421 ; free virtual = 46315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 11383 ; free virtual = 46284 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 11381 ; free virtual = 46283 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 11319 ; free virtual = 46236 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------ Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11332 ; free virtual = 46230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 11324 ; free virtual = 46216 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 11253 ; free virtual = 46165 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 11252 ; free virtual = 46164 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:18:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2455.867 ; gain = 343.105 ; free physical = 11214 ; free virtual = 46126 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:18:24 2019... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11454 ; free virtual = 46346 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 11476 ; free virtual = 46368 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20721 Creating bitstream... Loading site data... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 11765 ; free virtual = 46659 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 11750 ; free virtual = 46642 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 11741 ; free virtual = 46633 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11713 ; free virtual = 46605 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11813 ; free virtual = 46710 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11880 ; free virtual = 46777 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11956 ; free virtual = 46852 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11964 ; free virtual = 46860 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11966 ; free virtual = 46862 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11965 ; free virtual = 46862 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11964 ; free virtual = 46861 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 11964 ; free virtual = 46861 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 11966 ; free virtual = 46862 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Creating bitstream... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 11839 ; free virtual = 46736 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 11745 ; free virtual = 46643 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11735 ; free virtual = 46632 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 11724 ; free virtual = 46622 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:18:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2474.117 ; gain = 333.105 ; free physical = 11717 ; free virtual = 46616 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:18:34 2019... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11721 ; free virtual = 46621 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 11754 ; free virtual = 46655 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 12943 ; free virtual = 47843 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12951 ; free virtual = 47852 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 12926 ; free virtual = 47827 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 12921 ; free virtual = 47823 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 12917 ; free virtual = 47818 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 12917 ; free virtual = 47818 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 12915 ; free virtual = 47817 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 12913 ; free virtual = 47815 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 12911 ; free virtual = 47812 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 12903 ; free virtual = 47804 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 12903 ; free virtual = 47805 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12891 ; free virtual = 47793 --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12877 ; free virtual = 47779 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12878 ; free virtual = 47780 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 12875 ; free virtual = 47777 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12848 ; free virtual = 47750 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20856 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 12907 ; free virtual = 47809 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12888 ; free virtual = 47790 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12858 ; free virtual = 47760 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12831 ; free virtual = 47733 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12829 ; free virtual = 47731 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12849 ; free virtual = 47751 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12847 ; free virtual = 47749 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12847 ; free virtual = 47748 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12839 ; free virtual = 47741 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.961 ; free physical = 12840 ; free virtual = 47742 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 12797 ; free virtual = 47699 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:18:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2473.117 ; gain = 333.105 ; free physical = 12782 ; free virtual = 47683 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:18:37 2019... INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12783 ; free virtual = 47685 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] touch build/specimen_006/OK WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13926 ; free virtual = 48832 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13922 ; free virtual = 48828 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13896 ; free virtual = 48802 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13896 ; free virtual = 48802 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13893 ; free virtual = 48799 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13877 ; free virtual = 48783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13876 ; free virtual = 48782 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 13869 ; free virtual = 48775 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 13869 ; free virtual = 48776 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 13790 ; free virtual = 48697 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:16] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 13653 ; free virtual = 48560 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1546.961 ; gain = 0.000 ; free physical = 13678 ; free virtual = 48588 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:18:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1546.961 ; gain = 0.000 ; free physical = 13669 ; free virtual = 48582 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2468.152 ; gain = 338.105 ; free physical = 13673 ; free virtual = 48587 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 13682 ; free virtual = 48589 --------------------------------------------------------------------------------- INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:18:42 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 14648 ; free virtual = 49562 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 14652 ; free virtual = 49560 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 14652 ; free virtual = 49559 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 14651 ; free virtual = 49558 Bitstream size: 4243411 bytes No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 14646 ; free virtual = 49554 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 DONE Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 14645 ; free virtual = 49553 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14628 ; free virtual = 49536 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14470 ; free virtual = 49379 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14470 ; free virtual = 49378 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14467 ; free virtual = 49376 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14466 ; free virtual = 49375 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14465 ; free virtual = 49374 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14464 ; free virtual = 49373 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14464 ; free virtual = 49373 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14463 ; free virtual = 49372 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14464 ; free virtual = 49373 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 14461 ; free virtual = 49370 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 14353 ; free virtual = 49262 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Launching helper process for spawning children vivado processes INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Helper process launched with PID 21212 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1468.254 ; gain = 385.359 ; free physical = 14334 ; free virtual = 49243 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] Running DRC as a precondition to command place_design WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 14308 ; free virtual = 49217 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 14220 ; free virtual = 49130 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 14219 ; free virtual = 49129 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 14199 ; free virtual = 49108 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1546.957 ; gain = 0.000 ; free physical = 14126 ; free virtual = 49035 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1546.957 ; gain = 0.000 ; free physical = 14152 ; free virtual = 49061 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21300 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 13898 ; free virtual = 48807 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 13827 ; free virtual = 48737 --------------------------------------------------------------------------------- Starting Placer Task Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 13803 ; free virtual = 48712 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 13797 ; free virtual = 48707 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 13741 ; free virtual = 48650 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13715 ; free virtual = 48625 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13622 ; free virtual = 48531 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13618 ; free virtual = 48528 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13608 ; free virtual = 48518 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13606 ; free virtual = 48515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13604 ; free virtual = 48514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13603 ; free virtual = 48513 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13602 ; free virtual = 48512 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 13600 ; free virtual = 48510 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 13600 ; free virtual = 48510 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 13475 ; free virtual = 48385 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 13470 ; free virtual = 48380 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 13452 ; free virtual = 48361 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13445 ; free virtual = 48354 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13335 ; free virtual = 48245 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13333 ; free virtual = 48242 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13315 ; free virtual = 48225 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13306 ; free virtual = 48216 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13300 ; free virtual = 48210 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13297 ; free virtual = 48206 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13287 ; free virtual = 48196 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 13278 ; free virtual = 48188 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 13276 ; free virtual = 48186 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21447 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 13231 ; free virtual = 48142 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 13180 ; free virtual = 48090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 13180 ; free virtual = 48090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 13266 ; free virtual = 48176 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 13120 ; free virtual = 48030 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12653 ; free virtual = 47563 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 21502 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.449 ; gain = 0.000 ; free physical = 12644 ; free virtual = 47554 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12615 ; free virtual = 47525 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12611 ; free virtual = 47522 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12580 ; free virtual = 47490 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 12170 ; free virtual = 47080 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 12144 ; free virtual = 47055 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 12143 ; free virtual = 47054 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 12154 ; free virtual = 47064 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2003.164 ; gain = 456.203 ; free physical = 12157 ; free virtual = 47067 Phase 1.3 Build Placer Netlist Model Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 12164 ; free virtual = 47074 Phase 2 Final Placement Cleanup INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 12171 ; free virtual = 47081 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 12172 ; free virtual = 47082 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 12181 ; free virtual = 47091 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 12182 ; free virtual = 47092 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 12213 ; free virtual = 47123 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 12069 ; free virtual = 46979 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 12070 ; free virtual = 46980 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 12104 ; free virtual = 47014 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1552.859 ; gain = 0.000 ; free physical = 11946 ; free virtual = 46857 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.57 . Memory (MB): peak = 1552.859 ; gain = 0.000 ; free physical = 11943 ; free virtual = 46853 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 11929 ; free virtual = 46839 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 11924 ; free virtual = 46834 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 11883 ; free virtual = 46794 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.164 ; gain = 456.203 ; free physical = 11842 ; free virtual = 46752 Phase 1.4 Constrain Clocks/Macros INFO: Launching helper process for spawning children vivado processes Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: Helper process launched with PID 21639 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 11826 ; free virtual = 46736 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11796 ; free virtual = 46706 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.164 ; gain = 456.203 ; free physical = 11770 ; free virtual = 46680 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.164 ; gain = 456.203 ; free physical = 11709 ; free virtual = 46620 Phase 2 Global Placement --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 11670 ; free virtual = 46580 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11612 ; free virtual = 46523 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11612 ; free virtual = 46522 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11612 ; free virtual = 46522 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11611 ; free virtual = 46521 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11612 ; free virtual = 46522 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11611 ; free virtual = 46521 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11611 ; free virtual = 46521 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.445 ; gain = 0.000 ; free physical = 11611 ; free virtual = 46521 Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11615 ; free virtual = 46526 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 11618 ; free virtual = 46529 INFO: [Project 1-571] Translating synthesized netlist Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:83] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:16] INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:7] INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 11417 ; free virtual = 46332 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 11404 ; free virtual = 46319 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11390 ; free virtual = 46301 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11407 ; free virtual = 46318 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2003.160 ; gain = 456.203 ; free physical = 11409 ; free virtual = 46320 Phase 1.3 Build Placer Netlist Model INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11389 ; free virtual = 46301 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11393 ; free virtual = 46304 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 11314 ; free virtual = 46224 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 11155 ; free virtual = 46065 --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 11109 ; free virtual = 46019 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11087 ; free virtual = 45998 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11084 ; free virtual = 45994 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11075 ; free virtual = 45985 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11076 ; free virtual = 45987 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11074 ; free virtual = 45985 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11073 ; free virtual = 45983 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11072 ; free virtual = 45983 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11069 ; free virtual = 45980 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 11072 ; free virtual = 45982 Phase 3.2 Commit Most Macros & LUTRAMs Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 11072 ; free virtual = 45982 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 11021 ; free virtual = 45932 Phase 3.3 Area Swap Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 11014 ; free virtual = 45925 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 11002 ; free virtual = 45913 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10960 ; free virtual = 45871 Phase 3.5 Small Shape Detail Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10953 ; free virtual = 45864 Phase 1.3 Build Placer Netlist Model INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10932 ; free virtual = 45843 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10931 ; free virtual = 45842 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:81] Phase 1 Placer Initialization | Checksum: eaaa372b WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:120] Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10929 ; free virtual = 45839 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:146] Phase 2 Final Placement Cleanup WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10898 ; free virtual = 45809 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10882 ; free virtual = 45793 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 10881 ; free virtual = 45791 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 10814 ; free virtual = 45726 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.160 ; gain = 456.203 ; free physical = 10820 ; free virtual = 45731 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 10803 ; free virtual = 45714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 10803 ; free virtual = 45714 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.160 ; gain = 456.203 ; free physical = 10800 ; free virtual = 45712 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10796 ; free virtual = 45707 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10772 ; free virtual = 45683 Phase 3.7 Pipeline Register Optimization Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.160 ; gain = 456.203 ; free physical = 10765 ; free virtual = 45676 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 10749 ; free virtual = 45661 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 No constraint files found. Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10746 ; free virtual = 45657 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 1 Build RT Design Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10709 ; free virtual = 45620 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 10724 ; free virtual = 45635 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10705 ; free virtual = 45616 Phase 4.2 Post Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10637 ; free virtual = 45548 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10606 ; free virtual = 45517 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 10580 ; free virtual = 45492 --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10574 ; free virtual = 45485 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10568 ; free virtual = 45480 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 10589 ; free virtual = 45500 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 10587 ; free virtual = 45498 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.211 ; gain = 552.250 ; free physical = 10580 ; free virtual = 45491 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.211 ; gain = 631.953 ; free physical = 10583 ; free virtual = 45495 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully INFO: [DRC 23-27] Running DRC with 8 threads synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 10595 ; free virtual = 45506 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 10469 ; free virtual = 45380 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 10468 ; free virtual = 45380 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10455 ; free virtual = 45367 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10487 ; free virtual = 45403 --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10493 ; free virtual = 45404 Phase 3.2 Commit Most Macros & LUTRAMs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10491 ; free virtual = 45403 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10490 ; free virtual = 45402 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10489 ; free virtual = 45401 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 10449 ; free virtual = 45361 --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10439 ; free virtual = 45351 Phase 3.3 Area Swap Optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 10423 ; free virtual = 45334 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10413 ; free virtual = 45325 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10389 ; free virtual = 45300 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10356 ; free virtual = 45268 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10310 ; free virtual = 45221 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10309 ; free virtual = 45221 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10308 ; free virtual = 45220 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10308 ; free virtual = 45220 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10308 ; free virtual = 45219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10307 ; free virtual = 45219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10307 ; free virtual = 45219 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10306 ; free virtual = 45217 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 10307 ; free virtual = 45219 INFO: [Project 1-571] Translating synthesized netlist Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10165 ; free virtual = 45076 Phase 3.6 Re-assign LUT pins Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10134 ; free virtual = 45045 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10134 ; free virtual = 45046 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 10106 ; free virtual = 45017 --------------------------------------------------------------------------------- Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10087 ; free virtual = 44999 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Project 1-570] Preparing netlist for logic optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 10039 ; free virtual = 44950 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 4.1 Post Commit Optimization | Checksum: 181723f81 --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 10032 ; free virtual = 44943 Phase 4.2 Post Placement Cleanup --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 10010 ; free virtual = 44922 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 9954 ; free virtual = 44865 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 9798 ; free virtual = 44710 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 9734 ; free virtual = 44646 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 9709 ; free virtual = 44621 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.203 ; gain = 0.000 ; free physical = 9740 ; free virtual = 44651 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 552.250 ; free physical = 9716 ; free virtual = 44628 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.207 ; gain = 630.953 ; free physical = 9716 ; free virtual = 44627 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9656 ; free virtual = 44567 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9680 ; free virtual = 44592 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9677 ; free virtual = 44589 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9676 ; free virtual = 44588 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9670 ; free virtual = 44582 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9670 ; free virtual = 44581 --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9667 ; free virtual = 44579 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9666 ; free virtual = 44577 Phase 2 Final Placement Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9662 ; free virtual = 44573 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9662 ; free virtual = 44573 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9661 ; free virtual = 44572 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9659 ; free virtual = 44571 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9651 ; free virtual = 44562 Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9651 ; free virtual = 44562 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 9651 ; free virtual = 44562 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 580.562 ; free physical = 9648 ; free virtual = 44560 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [Project 1-571] Translating synthesized netlist INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 9006 ; free virtual = 43917 Starting Routing Task Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1906.438 ; gain = 0.000 ; free physical = 8980 ; free virtual = 43892 Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 8979 ; free virtual = 43891 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 8962 ; free virtual = 43874 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 8925 ; free virtual = 43837 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8915 ; free virtual = 43826 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 8858 ; free virtual = 43769 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16bd26d57 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 8860 ; free virtual = 43772 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8829 ; free virtual = 43741 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8829 ; free virtual = 43740 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8831 ; free virtual = 43743 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8831 ; free virtual = 43742 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8837 ; free virtual = 43748 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8838 ; free virtual = 43750 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8840 ; free virtual = 43751 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2004.152 ; gain = 456.203 ; free physical = 8842 ; free virtual = 43754 Phase 1.3 Build Placer Netlist Model Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 8842 ; free virtual = 43754 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 8844 ; free virtual = 43756 INFO: [Project 1-571] Translating synthesized netlist Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 8835 ; free virtual = 43747 Phase 1.3 Build Placer Netlist Model INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 8696 ; free virtual = 43608 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.152 ; gain = 456.203 ; free physical = 8612 ; free virtual = 43524 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.152 ; gain = 456.203 ; free physical = 8550 ; free virtual = 43462 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1481.746 ; gain = 0.000 ; free physical = 8535 ; free virtual = 43447 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.152 ; gain = 456.203 ; free physical = 8534 ; free virtual = 43445 Phase 2 Global Placement Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1481.746 ; gain = 0.000 ; free physical = 8528 ; free virtual = 43440 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 8537 ; free virtual = 43449 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 8463 ; free virtual = 43374 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 8429 ; free virtual = 43341 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 8401 ; free virtual = 43313 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 8374 ; free virtual = 43286 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 8332 ; free virtual = 43244 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 8355 ; free virtual = 43266 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Placer Task Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1464.723 ; gain = 0.000 ; free physical = 8347 ; free virtual = 43259 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1464.723 ; gain = 0.000 ; free physical = 8347 ; free virtual = 43259 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 7992 ; free virtual = 42904 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 7997 ; free virtual = 42908 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 7982 ; free virtual = 42893 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 7974 ; free virtual = 42886 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 7970 ; free virtual = 42882 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 7946 ; free virtual = 42858 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 7942 ; free virtual = 42853 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 7940 ; free virtual = 42852 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7856 ; free virtual = 42767 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7782 ; free virtual = 42694 Phase 3.2 Commit Most Macros & LUTRAMs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 7770 ; free virtual = 42682 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7756 ; free virtual = 42667 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7750 ; free virtual = 42661 Phase 3.4 Pipeline Register Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7740 ; free virtual = 42652 Phase 3.5 Small Shape Detail Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7737 ; free virtual = 42648 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7736 ; free virtual = 42647 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7730 ; free virtual = 42641 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7730 ; free virtual = 42641 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7730 ; free virtual = 42641 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7729 ; free virtual = 42641 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 7729 ; free virtual = 42641 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7631 ; free virtual = 42542 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7624 ; free virtual = 42535 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7615 ; free virtual = 42527 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7607 ; free virtual = 42519 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7603 ; free virtual = 42514 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7598 ; free virtual = 42510 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7593 ; free virtual = 42504 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7588 ; free virtual = 42500 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7583 ; free virtual = 42494 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2100.199 ; gain = 552.250 ; free physical = 7599 ; free virtual = 42510 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2100.199 ; gain = 631.953 ; free physical = 7595 ; free virtual = 42507 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: cea32407 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.957 ; gain = 41.668 ; free physical = 7138 ; free virtual = 42050 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: cea32407 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.945 ; gain = 47.656 ; free physical = 7062 ; free virtual = 41973 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: cea32407 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2072.945 ; gain = 47.656 ; free physical = 7053 ; free virtual = 41964 INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.250 ; gain = 60.961 ; free physical = 6898 ; free virtual = 41809 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1909.457 ; gain = 0.000 ; free physical = 6878 ; free virtual = 41789 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 6860 ; free virtual = 41772 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 6854 ; free virtual = 41766 Phase 4 Rip-up And Reroute | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 6854 ; free virtual = 41766 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 6854 ; free virtual = 41765 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 6853 ; free virtual = 41764 Phase 6 Post Hold Fix | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 6853 ; free virtual = 41764 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 6843 ; free virtual = 41754 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 6842 ; free virtual = 41754 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 6836 ; free virtual = 41748 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 6874 ; free virtual = 41786 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2129.039 ; gain = 135.766 ; free physical = 6873 ; free virtual = 41785 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2129.039 ; gain = 0.000 ; free physical = 6896 ; free virtual = 41811 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1487277ac Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 6897 ; free virtual = 41812 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 6896 ; free virtual = 41811 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 6896 ; free virtual = 41811 Phase 1 Placer Initialization | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 6896 ; free virtual = 41811 Phase 2 Global Placement INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Global Placement | Checksum: 1d7ade655 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6443 ; free virtual = 41355 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d7ade655 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6434 ; free virtual = 41346 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 24340a58a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6422 ; free virtual = 41335 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d1b8355 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6378 ; free virtual = 41290 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e6cfe3ba Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6363 ; free virtual = 41275 Phase 3.5 Small Shape Detail Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.234 ; gain = 0.000 ; free physical = 6314 ; free virtual = 41227 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.5 Small Shape Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6330 ; free virtual = 41243 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6309 ; free virtual = 41222 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6298 ; free virtual = 41210 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 6289 ; free virtual = 41202 Phase 1.3 Build Placer Netlist Model Phase 3 Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6281 ; free virtual = 41193 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6252 ; free virtual = 41164 Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 6247 ; free virtual = 41160 Phase 1.4 Constrain Clocks/Macros Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6214 ; free virtual = 41127 Phase 4.3 Placer Reporting Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 6219 ; free virtual = 41131 Phase 4.3 Placer Reporting | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6213 ; free virtual = 41125 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6198 ; free virtual = 41111 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6183 ; free virtual = 41096 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 6185 ; free virtual = 41097 Phase 2 Final Placement Cleanup Ending Placer Task | Checksum: 163bdd4e6 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 6177 ; free virtual = 41090 Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 6176 ; free virtual = 41089 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 2093.547 ; gain = 668.609 ; free physical = 6177 ; free virtual = 41089 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 6126 ; free virtual = 41038 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1993.277 ; gain = 576.562 ; free physical = 6120 ; free virtual = 41033 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 6081 ; free virtual = 40993 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 467.531 ; free physical = 6062 ; free virtual = 40975 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 467.531 ; free physical = 6059 ; free virtual = 40971 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 467.531 ; free physical = 6059 ; free virtual = 40971 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 467.531 ; free physical = 6058 ; free virtual = 40970 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 467.531 ; free physical = 6057 ; free virtual = 40969 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 467.531 ; free physical = 6056 ; free virtual = 40968 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 6056 ; free virtual = 40968 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 7f1e2bdc ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 5789 ; free virtual = 40702 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 5757 ; free virtual = 40670 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 5756 ; free virtual = 40669 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 5732 ; free virtual = 40644 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 5726 ; free virtual = 40638 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 5725 ; free virtual = 40638 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 5725 ; free virtual = 40637 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 5724 ; free virtual = 40637 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 5724 ; free virtual = 40637 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 5724 ; free virtual = 40637 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 5726 ; free virtual = 40639 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 5726 ; free virtual = 40638 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 5717 ; free virtual = 40629 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 5755 ; free virtual = 40667 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2127.254 ; gain = 135.766 ; free physical = 5755 ; free virtual = 40667 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 5746 ; free virtual = 40662 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2129.438 ; gain = 30.227 ; free physical = 5762 ; free virtual = 40674 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.426 ; gain = 37.215 ; free physical = 5727 ; free virtual = 40640 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.426 ; gain = 37.215 ; free physical = 5727 ; free virtual = 40640 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5610 ; free virtual = 40523 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5592 ; free virtual = 40505 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5588 ; free virtual = 40501 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5588 ; free virtual = 40501 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5588 ; free virtual = 40501 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5588 ; free virtual = 40501 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5588 ; free virtual = 40501 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5577 ; free virtual = 40490 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5576 ; free virtual = 40489 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5576 ; free virtual = 40489 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2156.480 ; gain = 57.270 ; free physical = 5610 ; free virtual = 40523 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:52 . Memory (MB): peak = 2195.270 ; gain = 96.059 ; free physical = 5610 ; free virtual = 40523 Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2195.270 ; gain = 0.000 ; free physical = 5302 ; free virtual = 40238 Loading route data... Processing options... Creating bitmap... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.930 ; gain = 45.668 ; free physical = 5251 ; free virtual = 40165 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.918 ; gain = 50.656 ; free physical = 5209 ; free virtual = 40124 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.918 ; gain = 50.656 ; free physical = 5209 ; free virtual = 40123 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 5154 ; free virtual = 40068 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 5101 ; free virtual = 40016 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 5100 ; free virtual = 40015 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 5101 ; free virtual = 40015 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 5101 ; free virtual = 40015 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 5101 ; free virtual = 40015 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 5101 ; free virtual = 40015 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 5094 ; free virtual = 40009 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 5094 ; free virtual = 40008 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 5088 ; free virtual = 40002 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 5122 ; free virtual = 40036 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2121.762 ; gain = 135.516 ; free physical = 5122 ; free virtual = 40036 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2121.762 ; gain = 0.000 ; free physical = 5121 ; free virtual = 40038 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2129.434 ; gain = 30.227 ; free physical = 5080 ; free virtual = 39995 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Running DRC as a precondition to command write_bitstream Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2135.422 ; gain = 36.215 ; free physical = 5039 ; free virtual = 39954 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2135.422 ; gain = 36.215 ; free physical = 5039 ; free virtual = 39954 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4949 ; free virtual = 39864 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4977 ; free virtual = 39892 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4972 ; free virtual = 39887 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4972 ; free virtual = 39887 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4972 ; free virtual = 39887 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4971 ; free virtual = 39886 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4971 ; free virtual = 39886 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4946 ; free virtual = 39861 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4944 ; free virtual = 39858 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4934 ; free virtual = 39849 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 4965 ; free virtual = 39879 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:56 . Memory (MB): peak = 2193.266 ; gain = 94.059 ; free physical = 4965 ; free virtual = 39879 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.266 ; gain = 0.000 ; free physical = 4751 ; free virtual = 39689 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.930 ; gain = 42.668 ; free physical = 4772 ; free virtual = 39692 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.918 ; gain = 48.656 ; free physical = 4742 ; free virtual = 39662 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.918 ; gain = 48.656 ; free physical = 4742 ; free virtual = 39662 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2077.973 ; gain = 58.711 ; free physical = 4717 ; free virtual = 39638 Phase 3 Initial Routing Phase 1 Build RT Design | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2134.074 ; gain = 49.668 ; free physical = 4702 ; free virtual = 39622 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 4620 ; free virtual = 39541 Phase 2.1 Fix Topology Constraints | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2143.062 ; gain = 58.656 ; free physical = 4614 ; free virtual = 39534 Phase 2.2 Pre Route Cleanup Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 4615 ; free virtual = 39535 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 4617 ; free virtual = 39537 Phase 5 Delay and Skew Optimization Phase 2.2 Pre Route Cleanup | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2143.062 ; gain = 58.656 ; free physical = 4618 ; free virtual = 39538 Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 4614 ; free virtual = 39535 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 4617 ; free virtual = 39537 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 4619 ; free virtual = 39540 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2079.973 ; gain = 60.711 ; free physical = 4611 ; free virtual = 39531 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 4610 ; free virtual = 39530 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 4650 ; free virtual = 39570 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 4691 ; free virtual = 39611 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2120.762 ; gain = 133.516 ; free physical = 4691 ; free virtual = 39611 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2120.762 ; gain = 0.000 ; free physical = 4671 ; free virtual = 39594 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:20:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 2 Router Initialization | Checksum: 130bdaadd Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 4598 ; free virtual = 39519 Phase 3 Initial Routing 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2469.145 ; gain = 340.105 ; free physical = 4603 ; free virtual = 39523 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:20:28 2019... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 4680 ; free virtual = 39600 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5353 ; free virtual = 40273 Phase 1 Build RT Design | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 5401 ; free virtual = 40322 Phase 4 Rip-up And Reroute | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5543 ; free virtual = 40463 Phase 5 Delay and Skew Optimization Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 5 Delay and Skew Optimization | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5522 ; free virtual = 40442 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 5505 ; free virtual = 40425 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 5504 ; free virtual = 40424 Phase 6.1 Hold Fix Iter | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5492 ; free virtual = 40413 Bitstream size: 4243411 bytes Config size: 1060815 words Phase 6 Post Hold Fix | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5493 ; free virtual = 40414 Number of configuration frames: 9996 Phase 7 Route finalize Running DRC as a precondition to command write_bitstream DONE Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5517 ; free virtual = 40438 Phase 8 Verifying routed nets Verification completed successfully INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 106d813e1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 5528 ; free virtual = 40449 Phase 3 Initial Routing Phase 8 Verifying routed nets | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5527 ; free virtual = 40448 Phase 9 Depositing Routes touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 5462 ; free virtual = 40384 Writing bitstream ./design.bit... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 5450 ; free virtual = 40373 Phase 4 Rip-up And Reroute | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 5450 ; free virtual = 40372 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 5445 ; free virtual = 40368 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 5445 ; free virtual = 40367 Phase 6 Post Hold Fix | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 5444 ; free virtual = 40367 Phase 7 Route finalize Phase 9 Depositing Routes | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5435 ; free virtual = 40358 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 5469 ; free virtual = 40393 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2217.281 ; gain = 164.891 ; free physical = 5468 ; free virtual = 40391 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 5478 ; free virtual = 40402 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 5476 ; free virtual = 40400 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 5473 ; free virtual = 40398 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 5502 ; free virtual = 40427 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 5502 ; free virtual = 40427 Loading data files... Writing placer database... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 5476 ; free virtual = 40406 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:20:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2462.430 ; gain = 335.176 ; free physical = 5452 ; free virtual = 40398 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:20:34 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.281 ; gain = 0.000 ; free physical = 6390 ; free virtual = 41345 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2131.426 ; gain = 31.227 ; free physical = 6341 ; free virtual = 41296 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2137.414 ; gain = 37.215 ; free physical = 6263 ; free virtual = 41218 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2137.414 ; gain = 37.215 ; free physical = 6262 ; free virtual = 41218 Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6265 ; free virtual = 41223 Phase 3 Initial Routing INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2217.281 ; gain = 0.000 ; free physical = 6248 ; free virtual = 41178 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6282 ; free virtual = 41213 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6278 ; free virtual = 41208 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6278 ; free virtual = 41208 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6278 ; free virtual = 41208 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6278 ; free virtual = 41208 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6278 ; free virtual = 41208 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6285 ; free virtual = 41215 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6284 ; free virtual = 41215 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6281 ; free virtual = 41212 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2156.469 ; gain = 56.270 ; free physical = 6314 ; free virtual = 41245 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 2195.258 ; gain = 95.059 ; free physical = 6313 ; free virtual = 41244 Writing placer database... Loading data files... Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2195.258 ; gain = 0.000 ; free physical = 6303 ; free virtual = 41261 Loading site data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:20:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2532.375 ; gain = 337.105 ; free physical = 6211 ; free virtual = 41147 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:20:42 2019... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 Writing bitstream ./design.bit... Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 15c4992dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.961 ; gain = 42.668 ; free physical = 7282 ; free virtual = 42222 Phase 1 Build RT Design | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2093.547 ; gain = 0.000 ; free physical = 7275 ; free virtual = 42215 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15c4992dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2073.949 ; gain = 48.656 ; free physical = 7271 ; free virtual = 42211 Phase 2.2 Pre Route Cleanup Phase 2.1 Fix Topology Constraints | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2093.547 ; gain = 0.000 ; free physical = 7271 ; free virtual = 42211 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2093.547 ; gain = 0.000 ; free physical = 7271 ; free virtual = 42211 Phase 2.2 Pre Route Cleanup | Checksum: 15c4992dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2073.949 ; gain = 48.656 ; free physical = 7265 ; free virtual = 42205 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.254 ; gain = 60.961 ; free physical = 7107 ; free virtual = 42047 Phase 3 Initial Routing Phase 2 Router Initialization | Checksum: 100878403 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 7107 ; free virtual = 42047 Phase 3 Initial Routing INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 7065 ; free virtual = 42005 Number of Nodes with overlaps = 0 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 3 Initial Routing | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7047 ; free virtual = 41987 Phase 4.1 Global Iteration 0 | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 7045 ; free virtual = 41986 Phase 4 Rip-up And Reroute | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 7044 ; free virtual = 41984 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 7042 ; free virtual = 41982 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 7040 ; free virtual = 41980 Phase 6 Post Hold Fix | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 7037 ; free virtual = 41978 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7030 ; free virtual = 41970 Phase 4 Rip-up And Reroute | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7022 ; free virtual = 41962 Phase 5 Delay and Skew Optimization Phase 7 Route finalize Phase 5 Delay and Skew Optimization | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7006 ; free virtual = 41947 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 6.1 Hold Fix Iter | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7001 ; free virtual = 41941 Phase 6 Post Hold Fix | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 6997 ; free virtual = 41937 Loading site data... Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize Phase 7 Route finalize | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 6988 ; free virtual = 41928 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 6990 ; free virtual = 41930 Phase 9 Depositing Routes Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Writing bitstream ./design.bit... Phase 9 Depositing Routes | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 6972 ; free virtual = 41913 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 7.684 ; free physical = 7006 ; free virtual = 41948 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2140.020 ; gain = 46.473 ; free physical = 7005 ; free virtual = 41946 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b213fb45 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7011 ; free virtual = 41952 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b213fb45 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 7025 ; free virtual = 41967 Phase 9 Depositing Routes Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:20:48 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading data files... Phase 9 Depositing Routes | Checksum: 1b213fb45 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 7071 ; free virtual = 42016 Writing XDEF routing. INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 7119 ; free virtual = 42065 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2130.043 ; gain = 136.766 ; free physical = 7135 ; free virtual = 42080 Writing XDEF routing logical nets. Writing XDEF routing special nets. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2461.867 ; gain = 340.105 ; free physical = 7144 ; free virtual = 42090 Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 7151 ; free virtual = 42097 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:20:48 2019... Loading route data... Processing options... Creating bitmap... Loading site data... Writing placer database... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Loading route data... Processing options... Creating bitmap... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.68 . Memory (MB): peak = 2130.043 ; gain = 0.000 ; free physical = 8250 ; free virtual = 43197 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2057.938 ; gain = 93.668 ; free physical = 8073 ; free virtual = 43019 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2062.926 ; gain = 98.656 ; free physical = 8057 ; free virtual = 43003 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2062.926 ; gain = 98.656 ; free physical = 8056 ; free virtual = 43002 Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8006 ; free virtual = 42952 Phase 3 Initial Routing Creating bitstream... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8013 ; free virtual = 42959 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8107 ; free virtual = 43053 Phase 4 Rip-up And Reroute | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8108 ; free virtual = 43054 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8108 ; free virtual = 43054 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8108 ; free virtual = 43054 Phase 6 Post Hold Fix | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 8108 ; free virtual = 43054 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 8092 ; free virtual = 43038 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 8090 ; free virtual = 43036 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 8092 ; free virtual = 43038 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 8123 ; free virtual = 43069 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2110.770 ; gain = 178.516 ; free physical = 8122 ; free virtual = 43068 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 8032 ; free virtual = 42980 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:20:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.371 ; gain = 339.105 ; free physical = 7974 ; free virtual = 42920 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:20:53 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25640 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Writing bitstream ./design.bit... Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:20:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2454.867 ; gain = 344.105 ; free physical = 8611 ; free virtual = 43570 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:20:59 2019... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25714 Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:21:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:34 . Memory (MB): peak = 2459.867 ; gain = 339.105 ; free physical = 9365 ; free virtual = 44325 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:21:02 2019... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 10221 ; free virtual = 45186 --------------------------------------------------------------------------------- Loading site data... Loading route data... Loading site data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25871 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:21:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.863 ; gain = 337.605 ; free physical = 9988 ; free virtual = 44953 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:21:12 2019... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10933 ; free virtual = 45898 --------------------------------------------------------------------------------- Creating bitstream... Writing bitstream ./design.bit... WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:16] Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Helper process launched with PID 25982 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:21 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 11471 ; free virtual = 46445 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11500 ; free virtual = 46480 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11476 ; free virtual = 46457 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11473 ; free virtual = 46454 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:21 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 11476 ; free virtual = 46451 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:21 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 11476 ; free virtual = 46451 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11482 ; free virtual = 46457 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:21:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2473.125 ; gain = 333.105 ; free physical = 11510 ; free virtual = 46488 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:21:19 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:21:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2453.875 ; gain = 343.105 ; free physical = 12492 ; free virtual = 47470 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:21:19 2019... touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Config size: 1060815 words --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 13430 ; free virtual = 48408 --------------------------------------------------------------------------------- Number of configuration frames: 9996 DONE Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 13436 ; free virtual = 48414 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26163 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 13659 ; free virtual = 48643 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:21:21 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:45 . Memory (MB): peak = 2607.402 ; gain = 390.121 ; free physical = 13649 ; free virtual = 48633 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:21:22 2019... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 13682 ; free virtual = 48664 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 13682 ; free virtual = 48664 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 13715 ; free virtual = 48697 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 14555 ; free virtual = 49549 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 14549 ; free virtual = 49538 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 14528 ; free virtual = 49516 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14511 ; free virtual = 49499 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 14486 ; free virtual = 49474 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:21:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2468.148 ; gain = 338.105 ; free physical = 14495 ; free virtual = 49483 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:21:24 2019... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 14506 ; free virtual = 49494 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15397 ; free virtual = 50386 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15397 ; free virtual = 50385 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15385 ; free virtual = 50374 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15351 ; free virtual = 50339 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string --------------------------------------------------------------------------------- Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15371 ; free virtual = 50360 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15367 ; free virtual = 50356 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15365 ; free virtual = 50354 WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15363 ; free virtual = 50352 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15362 ; free virtual = 50351 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 15364 ; free virtual = 50352 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: Launching helper process for spawning children vivado processes INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] INFO: Helper process launched with PID 26277 touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 15364 ; free virtual = 50354 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 15373 ; free virtual = 50363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 15371 ; free virtual = 50362 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 15327 ; free virtual = 50317 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15275 ; free virtual = 50265 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15261 ; free virtual = 50251 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15243 ; free virtual = 50236 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15241 ; free virtual = 50234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15236 ; free virtual = 50230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15234 ; free virtual = 50228 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15232 ; free virtual = 50227 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 15229 ; free virtual = 50224 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 15229 ; free virtual = 50224 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26364 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 15063 ; free virtual = 50058 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 15058 ; free virtual = 50053 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 15039 ; free virtual = 50034 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14908 ; free virtual = 49904 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14909 ; free virtual = 49904 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14902 ; free virtual = 49898 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14890 ; free virtual = 49885 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14889 ; free virtual = 49884 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14888 ; free virtual = 49883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14885 ; free virtual = 49880 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 14885 ; free virtual = 49880 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14857 ; free virtual = 49853 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 14857 ; free virtual = 49852 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 14787 ; free virtual = 49782 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Starting Placer Task INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] Phase 1 Placer Initialization WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] Phase 1.1 Placer Initialization Netlist Sorting WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1272] Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 14603 ; free virtual = 49598 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 14596 ; free virtual = 49591 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 14453 ; free virtual = 49448 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 14437 ; free virtual = 49433 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14357 ; free virtual = 49353 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 14367 ; free virtual = 49362 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26434 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14109 ; free virtual = 49104 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14182 ; free virtual = 49178 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14200 ; free virtual = 49195 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14199 ; free virtual = 49194 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14198 ; free virtual = 49193 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14198 ; free virtual = 49193 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14197 ; free virtual = 49192 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 14189 ; free virtual = 49185 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 14190 ; free virtual = 49186 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 14182 ; free virtual = 49178 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 14203 ; free virtual = 49201 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 14188 ; free virtual = 49184 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 14183 ; free virtual = 49179 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 14185 ; free virtual = 49182 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 14171 ; free virtual = 49167 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 14122 ; free virtual = 49118 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Placer Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 14105 ; free virtual = 49101 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 14097 ; free virtual = 49093 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1667] INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.961 ; gain = 0.000 ; free physical = 13932 ; free virtual = 48928 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1547.961 ; gain = 0.000 ; free physical = 13910 ; free virtual = 48915 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 13986 ; free virtual = 48982 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 13931 ; free virtual = 48928 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 13932 ; free virtual = 48929 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 13892 ; free virtual = 48888 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26517 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26518 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 13748 ; free virtual = 48745 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.965 ; gain = 0.000 ; free physical = 13581 ; free virtual = 48577 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1471.965 ; gain = 0.000 ; free physical = 13578 ; free virtual = 48574 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 13491 ; free virtual = 48488 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26610 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1305.930 ; gain = 210.480 ; free physical = 13333 ; free virtual = 48330 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1305.930 ; gain = 210.480 ; free physical = 13372 ; free virtual = 48370 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13358 ; free virtual = 48359 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 13377 ; free virtual = 48385 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 13349 ; free virtual = 48364 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 13349 ; free virtual = 48364 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 13341 ; free virtual = 48358 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 13309 ; free virtual = 48308 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13307 ; free virtual = 48306 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13307 ; free virtual = 48306 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13306 ; free virtual = 48305 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13306 ; free virtual = 48305 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13305 ; free virtual = 48304 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13305 ; free virtual = 48304 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13304 ; free virtual = 48303 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 13305 ; free virtual = 48304 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.914 ; gain = 218.457 ; free physical = 13308 ; free virtual = 48307 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 13194 ; free virtual = 48193 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 13183 ; free virtual = 48182 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 13152 ; free virtual = 48151 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 13059 ; free virtual = 48058 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 13033 ; free virtual = 48032 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26654 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12787 ; free virtual = 47785 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12775 ; free virtual = 47774 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12768 ; free virtual = 47767 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12766 ; free virtual = 47765 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12762 ; free virtual = 47761 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12760 ; free virtual = 47759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12757 ; free virtual = 47756 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12748 ; free virtual = 47747 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 12748 ; free virtual = 47747 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 12630 ; free virtual = 47628 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 12562 ; free virtual = 47560 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 12515 ; free virtual = 47513 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 12447 ; free virtual = 47446 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 12435 ; free virtual = 47434 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 12432 ; free virtual = 47430 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 12421 ; free virtual = 47419 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 12417 ; free virtual = 47415 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Ending Placer Task | Checksum: cd729a62 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 12415 ; free virtual = 47414 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 12415 ; free virtual = 47413 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Command: route_design Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:251] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:811] Running DRC as a precondition to command route_design WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:951] Command: report_drc (run_mandatory_drcs) for: router_checks WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1091] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1404.930 ; gain = 322.039 ; free physical = 12440 ; free virtual = 47439 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 12436 ; free virtual = 47435 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 12414 ; free virtual = 47413 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 12412 ; free virtual = 47411 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.949 ; gain = 115.504 ; free physical = 12356 ; free virtual = 47355 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Start Part Resource Summary --------------------------------------------------------------------------------- Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:55] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 12354 ; free virtual = 47353 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 12374 ; free virtual = 47374 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 12345 ; free virtual = 47344 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 12344 ; free virtual = 47343 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.961 ; gain = 0.000 ; free physical = 12334 ; free virtual = 47333 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1470.961 ; gain = 0.000 ; free physical = 12327 ; free virtual = 47326 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 12296 ; free virtual = 47296 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12189 ; free virtual = 47188 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12168 ; free virtual = 47167 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12158 ; free virtual = 47157 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 12162 ; free virtual = 47162 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11926 ; free virtual = 46925 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11918 ; free virtual = 46918 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11916 ; free virtual = 46915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11906 ; free virtual = 46905 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11902 ; free virtual = 46901 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11899 ; free virtual = 46899 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11895 ; free virtual = 46895 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11885 ; free virtual = 46884 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 11886 ; free virtual = 46885 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1296] INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2208] INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 11565 ; free virtual = 46565 --------------------------------------------------------------------------------- 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 11604 ; free virtual = 46604 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 11603 ; free virtual = 46603 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 11559 ; free virtual = 46558 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 11463 ; free virtual = 46463 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 11416 ; free virtual = 46416 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 11383 ; free virtual = 46383 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 11365 ; free virtual = 46364 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 11330 ; free virtual = 46330 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 11322 ; free virtual = 46321 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 11323 ; free virtual = 46322 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 11271 ; free virtual = 46270 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 11262 ; free virtual = 46261 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 11258 ; free virtual = 46257 INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 11213 ; free virtual = 46213 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.449 ; gain = 0.000 ; free physical = 11205 ; free virtual = 46205 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2064] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2112] Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 10919 ; free virtual = 45918 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2136] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 10904 ; free virtual = 45903 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 10870 ; free virtual = 45869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 10866 ; free virtual = 45865 --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 10864 ; free virtual = 45864 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 10840 ; free virtual = 45840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 10825 ; free virtual = 45825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: INFO: [DRC 23-27] Running DRC with 8 threads +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 10820 ; free virtual = 45820 Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 10820 ; free virtual = 45820 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 10801 ; free virtual = 45801 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 10795 ; free virtual = 45795 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 10632 ; free virtual = 45632 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 10615 ; free virtual = 45615 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10595 ; free virtual = 45595 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.453 ; gain = 0.000 ; free physical = 10614 ; free virtual = 45614 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 10597 ; free virtual = 45597 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10588 ; free virtual = 45587 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10587 ; free virtual = 45587 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 10584 ; free virtual = 45584 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10577 ; free virtual = 45577 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 519.531 ; free physical = 10575 ; free virtual = 45575 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10572 ; free virtual = 45571 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10571 ; free virtual = 45570 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.496 ; gain = 519.531 ; free physical = 10570 ; free virtual = 45570 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10570 ; free virtual = 45570 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10570 ; free virtual = 45570 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10570 ; free virtual = 45569 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10570 ; free virtual = 45569 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10569 ; free virtual = 45568 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 10569 ; free virtual = 45569 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 10569 ; free virtual = 45569 Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.496 ; gain = 519.531 ; free physical = 10571 ; free virtual = 45570 Phase 1 Placer Initialization | Checksum: eaaa372b INFO: [Project 1-571] Translating synthesized netlist Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.496 ; gain = 519.531 ; free physical = 10569 ; free virtual = 45569 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.496 ; gain = 519.531 ; free physical = 10554 ; free virtual = 45553 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.496 ; gain = 519.531 ; free physical = 10552 ; free virtual = 45551 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.496 ; gain = 584.562 ; free physical = 10551 ; free virtual = 45550 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10462 ; free virtual = 45461 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10461 ; free virtual = 45460 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10461 ; free virtual = 45460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10462 ; free virtual = 45461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10462 ; free virtual = 45462 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10462 ; free virtual = 45462 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10461 ; free virtual = 45461 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10464 ; free virtual = 45464 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 10466 ; free virtual = 45465 INFO: [Project 1-571] Translating synthesized netlist Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 10452 ; free virtual = 45452 Phase 1.4 Constrain Clocks/Macros INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 10444 ; free virtual = 45444 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 10441 ; free virtual = 45440 Phase 2 Global Placement Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 10103 ; free virtual = 45102 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 10050 ; free virtual = 45050 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 10042 ; free virtual = 45042 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 3.3 Area Swap Optimization 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 10096 ; free virtual = 45096 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 10090 ; free virtual = 45094 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 10041 ; free virtual = 45052 Phase 3.5 Small Shape Detail Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 10001 ; free virtual = 45021 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 10017 ; free virtual = 45018 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 10020 ; free virtual = 45021 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: eeeca7b0 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 10017 ; free virtual = 45018 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9964 ; free virtual = 44985 Phase 3.6 Re-assign LUT pins report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9932 ; free virtual = 44953 Phase 3.7 Pipeline Register Optimization INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 9931 ; free virtual = 44952 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cf4d1b03 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 9914 ; free virtual = 44935 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9800 ; free virtual = 44821 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9690 ; free virtual = 44711 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 9646 ; free virtual = 44647 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 9645 ; free virtual = 44646 --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9639 ; free virtual = 44641 Phase 4.2 Post Placement Cleanup INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9614 ; free virtual = 44615 Phase 4.3 Placer Reporting INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.449 ; gain = 0.000 ; free physical = 9595 ; free virtual = 44596 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9577 ; free virtual = 44579 Phase 4.4 Final Placement Cleanup Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 515.531 ; free physical = 9549 ; free virtual = 44551 Phase 1.3 Build Placer Netlist Model Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9544 ; free virtual = 44546 Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 515.531 ; free physical = 9542 ; free virtual = 44544 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 515.531 ; free physical = 9540 ; free virtual = 44542 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 515.531 ; free physical = 9539 ; free virtual = 44540 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 515.531 ; free physical = 9536 ; free virtual = 44537 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 515.531 ; free physical = 9533 ; free virtual = 44534 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.492 ; gain = 581.562 ; free physical = 9532 ; free virtual = 44534 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9506 ; free virtual = 44507 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.207 ; gain = 543.246 ; free physical = 9542 ; free virtual = 44543 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.207 ; gain = 623.949 ; free physical = 9541 ; free virtual = 44543 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 9460 ; free virtual = 44463 --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 9317 ; free virtual = 44320 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 9314 ; free virtual = 44317 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.234 ; gain = 0.000 ; free physical = 9070 ; free virtual = 44073 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 9057 ; free virtual = 44060 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 9055 ; free virtual = 44059 Phase 1.3 Build Placer Netlist Model Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 9051 ; free virtual = 44054 Phase 1.4 Constrain Clocks/Macros No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 9048 ; free virtual = 44051 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 9046 ; free virtual = 44049 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 9041 ; free virtual = 44044 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 9040 ; free virtual = 44043 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 576.562 ; free physical = 9039 ; free virtual = 44042 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 8652 ; free virtual = 43655 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8547 ; free virtual = 43551 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8542 ; free virtual = 43545 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8541 ; free virtual = 43544 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8541 ; free virtual = 43544 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8540 ; free virtual = 43543 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8542 ; free virtual = 43545 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 8542 ; free virtual = 43545 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8537 ; free virtual = 43540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 8550 ; free virtual = 43553 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8531 ; free virtual = 43534 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 8428 ; free virtual = 43431 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8427 ; free virtual = 43430 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 8340 ; free virtual = 43343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8353 ; free virtual = 43356 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8372 ; free virtual = 43375 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8366 ; free virtual = 43369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8362 ; free virtual = 43366 --------------------------------------------------------------------------------- Starting Placer Task --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8363 ; free virtual = 43366 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8363 ; free virtual = 43366 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8363 ; free virtual = 43366 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8364 ; free virtual = 43367 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:42 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 8365 ; free virtual = 43369 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 8366 ; free virtual = 43369 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1555.855 ; gain = 0.000 ; free physical = 8344 ; free virtual = 43347 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.60 . Memory (MB): peak = 1555.855 ; gain = 0.000 ; free physical = 8329 ; free virtual = 43332 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8161 ; free virtual = 43164 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7719 ; free virtual = 42722 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7681 ; free virtual = 42684 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7566 ; free virtual = 42570 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 7558 ; free virtual = 42562 --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7543 ; free virtual = 42546 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7513 ; free virtual = 42516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7488 ; free virtual = 42491 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7487 ; free virtual = 42491 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7481 ; free virtual = 42484 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 7481 ; free virtual = 42484 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 7425 ; free virtual = 42429 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b1503975 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7416 ; free virtual = 42419 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7415 ; free virtual = 42418 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7414 ; free virtual = 42418 Phase 1 Placer Initialization | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7414 ; free virtual = 42417 Phase 2 Global Placement WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f35ea853 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7406 ; free virtual = 42410 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 18ab10e39 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7406 ; free virtual = 42409 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 18ab10e39 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7405 ; free virtual = 42408 Phase 1 Placer Initialization | Checksum: 18ab10e39 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7404 ; free virtual = 42407 Phase 2 Global Placement Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 7371 ; free virtual = 42374 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 7336 ; free virtual = 42340 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 7336 ; free virtual = 42339 Number of Nodes with overlaps = 0 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 7295 ; free virtual = 42298 Phase 3 Initial Routing WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Number of Nodes with overlaps = 0 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7286 ; free virtual = 42289 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7287 ; free virtual = 42290 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7287 ; free virtual = 42290 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7287 ; free virtual = 42290 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7289 ; free virtual = 42292 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7289 ; free virtual = 42292 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Project 1-570] Preparing netlist for logic optimization Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 7329 ; free virtual = 42332 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 7328 ; free virtual = 42331 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 7328 ; free virtual = 42332 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 7366 ; free virtual = 42370 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.254 ; gain = 136.766 ; free physical = 7366 ; free virtual = 42370 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 7392 ; free virtual = 42398 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 2408ba81e Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7375 ; free virtual = 42379 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2408ba81e Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7369 ; free virtual = 42373 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2559e6f74 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7362 ; free virtual = 42366 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22f794d3f Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7325 ; free virtual = 42329 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f92dada4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7318 ; free virtual = 42322 Phase 3.5 Small Shape Detail Placement Phase 2 Global Placement | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7334 ; free virtual = 42338 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7351 ; free virtual = 42355 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 251526ef8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7380 ; free virtual = 42384 Phase 3.3 Area Swap Optimization Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks Phase 3.3 Area Swap Optimization | Checksum: 22b2d4cc3 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7380 ; free virtual = 42384 Phase 3.4 Pipeline Register Optimization INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.4 Pipeline Register Optimization | Checksum: 1f4e1ad28 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7380 ; free virtual = 42384 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7378 ; free virtual = 42382 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7376 ; free virtual = 42380 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7375 ; free virtual = 42379 Phase 3 Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7370 ; free virtual = 42374 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7367 ; free virtual = 42371 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7367 ; free virtual = 42371 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7367 ; free virtual = 42371 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7365 ; free virtual = 42369 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7364 ; free virtual = 42368 Ending Placer Task | Checksum: fb45469f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7373 ; free virtual = 42377 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 7373 ; free virtual = 42377 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7374 ; free virtual = 42378 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7370 ; free virtual = 42374 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7367 ; free virtual = 42370 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 3 Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7363 ; free virtual = 42367 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7364 ; free virtual = 42368 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7361 ; free virtual = 42365 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7356 ; free virtual = 42360 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7352 ; free virtual = 42356 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7351 ; free virtual = 42355 Ending Placer Task | Checksum: 16e2e720d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 7358 ; free virtual = 42362 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2084.543 ; gain = 659.605 ; free physical = 7357 ; free virtual = 42361 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 16a59d95 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 898ec903 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 7208 ; free virtual = 42212 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 7146 ; free virtual = 42150 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 7140 ; free virtual = 42144 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 7096 ; free virtual = 42100 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 7048 ; free virtual = 42052 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 7046 ; free virtual = 42050 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 7046 ; free virtual = 42050 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 7046 ; free virtual = 42050 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 7045 ; free virtual = 42049 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 7045 ; free virtual = 42049 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 7064 ; free virtual = 42068 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.590 ; gain = 64.086 ; free physical = 7063 ; free virtual = 42067 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.590 ; gain = 65.086 ; free physical = 7057 ; free virtual = 42061 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.590 ; gain = 65.086 ; free physical = 7094 ; free virtual = 42098 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2127.379 ; gain = 135.891 ; free physical = 7091 ; free virtual = 42095 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2127.379 ; gain = 0.000 ; free physical = 7031 ; free virtual = 42038 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading data files... Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 6346 ; free virtual = 41351 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.180 ; gain = 43.668 ; free physical = 6283 ; free virtual = 41287 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.168 ; gain = 49.656 ; free physical = 6250 ; free virtual = 41255 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.168 ; gain = 49.656 ; free physical = 6250 ; free virtual = 41255 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 6190 ; free virtual = 41194 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 6191 ; free virtual = 41195 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.387 ; gain = 496.531 ; free physical = 6192 ; free virtual = 41196 Phase 1.3 Build Placer Netlist Model Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 6192 ; free virtual = 41196 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 6192 ; free virtual = 41196 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 6192 ; free virtual = 41196 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 6191 ; free virtual = 41196 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 6191 ; free virtual = 41196 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 6190 ; free virtual = 41195 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2087.473 ; gain = 63.961 ; free physical = 6188 ; free virtual = 41193 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2088.473 ; gain = 64.961 ; free physical = 6171 ; free virtual = 41176 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2088.473 ; gain = 64.961 ; free physical = 6209 ; free virtual = 41213 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2127.262 ; gain = 135.766 ; free physical = 6209 ; free virtual = 41213 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2127.262 ; gain = 0.000 ; free physical = 6206 ; free virtual = 41214 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:14 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 6167 ; free virtual = 41172 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 496.531 ; free physical = 6054 ; free virtual = 41059 Phase 1.4 Constrain Clocks/Macros Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1552.859 ; gain = 0.000 ; free physical = 6021 ; free virtual = 41026 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 496.531 ; free physical = 6018 ; free virtual = 41023 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.57 . Memory (MB): peak = 1552.859 ; gain = 0.000 ; free physical = 6054 ; free virtual = 41060 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:14 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 6064 ; free virtual = 41070 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 496.531 ; free physical = 6071 ; free virtual = 41076 Phase 2 Final Placement Cleanup INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2064.176 ; gain = 45.668 ; free physical = 6094 ; free virtual = 41099 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.164 ; gain = 50.656 ; free physical = 6056 ; free virtual = 41061 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.164 ; gain = 50.656 ; free physical = 6055 ; free virtual = 41060 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 496.531 ; free physical = 6039 ; free virtual = 41044 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 496.531 ; free physical = 6026 ; free virtual = 41031 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 6023 ; free virtual = 41029 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.219 ; gain = 60.711 ; free physical = 5989 ; free virtual = 40994 Phase 3 Initial Routing Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.219 ; gain = 62.711 ; free physical = 5895 ; free virtual = 40900 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.219 ; gain = 62.711 ; free physical = 5893 ; free virtual = 40899 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.219 ; gain = 62.711 ; free physical = 5891 ; free virtual = 40896 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.219 ; gain = 62.711 ; free physical = 5890 ; free virtual = 40895 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.219 ; gain = 62.711 ; free physical = 5888 ; free virtual = 40894 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.219 ; gain = 62.711 ; free physical = 5888 ; free virtual = 40893 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.219 ; gain = 62.711 ; free physical = 5827 ; free virtual = 40833 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.219 ; gain = 64.711 ; free physical = 5820 ; free virtual = 40825 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.219 ; gain = 64.711 ; free physical = 5799 ; free virtual = 40805 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.219 ; gain = 64.711 ; free physical = 5834 ; free virtual = 40840 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2122.008 ; gain = 135.516 ; free physical = 5832 ; free virtual = 40837 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2122.008 ; gain = 0.000 ; free physical = 5842 ; free virtual = 40850 Loading site data... Loading data files... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1553.863 ; gain = 0.000 ; free physical = 5786 ; free virtual = 40792 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.55 . Memory (MB): peak = 1553.863 ; gain = 0.000 ; free physical = 5803 ; free virtual = 40809 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2129.438 ; gain = 38.230 ; free physical = 5960 ; free virtual = 40970 INFO: [Vivado 12-1842] Bitgen Completed Successfully. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.426 ; gain = 44.219 ; free physical = 5972 ; free virtual = 40982 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.426 ; gain = 44.219 ; free physical = 5972 ; free virtual = 40982 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5930 ; free virtual = 40940 Phase 3 Initial Routing Creating bitstream... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5905 ; free virtual = 40915 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5895 ; free virtual = 40905 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5895 ; free virtual = 40905 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5895 ; free virtual = 40905 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5895 ; free virtual = 40905 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5894 ; free virtual = 40904 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5937 ; free virtual = 40947 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5935 ; free virtual = 40945 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5932 ; free virtual = 40941 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2154.480 ; gain = 63.273 ; free physical = 5967 ; free virtual = 40977 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:52 . Memory (MB): peak = 2193.270 ; gain = 102.062 ; free physical = 5966 ; free virtual = 40975 Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:23:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2471.359 ; gain = 343.105 ; free physical = 5812 ; free virtual = 40833 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:23:07 2019... Writing bitstream ./design.bit... Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_013 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 18a962264 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.961 ; gain = 41.668 ; free physical = 7138 ; free virtual = 42168 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18a962264 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.949 ; gain = 48.656 ; free physical = 7097 ; free virtual = 42127 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18a962264 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.949 ; gain = 48.656 ; free physical = 7096 ; free virtual = 42127 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.254 ; gain = 61.961 ; free physical = 6982 ; free virtual = 42016 Phase 3 Initial Routing Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.270 ; gain = 0.000 ; free physical = 6974 ; free virtual = 42011 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7017 ; free virtual = 42055 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7015 ; free virtual = 42052 Phase 4 Rip-up And Reroute | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7013 ; free virtual = 42051 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7012 ; free virtual = 42050 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7010 ; free virtual = 42048 Phase 6 Post Hold Fix | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 7009 ; free virtual = 42047 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 6975 ; free virtual = 42013 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 6961 ; free virtual = 42000 Phase 9 Depositing Routes INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 6987 ; free virtual = 42003 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 7020 ; free virtual = 42035 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2130.043 ; gain = 136.766 ; free physical = 7021 ; free virtual = 42037 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2130.043 ; gain = 0.000 ; free physical = 6916 ; free virtual = 41936 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 147c036e4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 6821 ; free virtual = 41837 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c036e4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 6746 ; free virtual = 41762 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c036e4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 6746 ; free virtual = 41762 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:23:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2471.484 ; gain = 344.105 ; free physical = 6707 ; free virtual = 41723 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:23:11 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 161e7cd46 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7045 ; free virtual = 42061 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Bitstream size: 4243411 bytes Command: report_drc (run_mandatory_drcs) for: bitstream_checks Config size: 1060815 words INFO: [DRC 23-27] Running DRC with 8 threads Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7709 ; free virtual = 42725 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7719 ; free virtual = 42735 Phase 4 Rip-up And Reroute | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7720 ; free virtual = 42736 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7721 ; free virtual = 42737 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7722 ; free virtual = 42738 Phase 6 Post Hold Fix | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7722 ; free virtual = 42738 Loading site data... Phase 7 Route finalize touch build/specimen_011/OK Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_014 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7747 ; free virtual = 42763 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7745 ; free virtual = 42761 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7746 ; free virtual = 42762 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7782 ; free virtual = 42798 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 7782 ; free virtual = 42798 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 7756 ; free virtual = 42774 Loading route data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Processing options... Creating bitmap... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading data files... Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 6862 ; free virtual = 41883 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:23:23 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2470.367 ; gain = 343.105 ; free physical = 6692 ; free virtual = 41713 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:23:23 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. touch build/specimen_012/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_015 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 7442 ; free virtual = 42463 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 7398 ; free virtual = 42420 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 7433 ; free virtual = 42454 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Creating bitstream... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 7401 ; free virtual = 42422 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 7401 ; free virtual = 42422 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174587064 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7330 ; free virtual = 42351 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7265 ; free virtual = 42286 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7262 ; free virtual = 42284 Phase 4 Rip-up And Reroute | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7252 ; free virtual = 42273 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7251 ; free virtual = 42273 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7251 ; free virtual = 42272 Phase 6 Post Hold Fix | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7250 ; free virtual = 42272 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7180 ; free virtual = 42202 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7178 ; free virtual = 42199 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7183 ; free virtual = 42205 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2103.227 ; gain = 10.684 ; free physical = 7219 ; free virtual = 42241 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2142.016 ; gain = 49.473 ; free physical = 7219 ; free virtual = 42240 Loading site data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.395 ; gain = 498.531 ; free physical = 7250 ; free virtual = 42271 Phase 1.3 Build Placer Netlist Model Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2142.016 ; gain = 0.000 ; free physical = 7139 ; free virtual = 42163 Phase 1 Build RT Design | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 7130 ; free virtual = 42154 Loading route data... Processing options... Creating bitmap... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 7139 ; free virtual = 42161 Phase 2.2 Pre Route Cleanup INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.2 Pre Route Cleanup | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 7138 ; free virtual = 42159 Loading site data... Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 129e3aa92 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 6985 ; free virtual = 42011 Phase 3 Initial Routing Loading route data... Running DRC as a precondition to command write_bitstream Processing options... Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitmap... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7156 ; free virtual = 42182 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7167 ; free virtual = 42192 Phase 4 Rip-up And Reroute | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7169 ; free virtual = 42195 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7206 ; free virtual = 42232 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7215 ; free virtual = 42241 Phase 6 Post Hold Fix | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7248 ; free virtual = 42274 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7303 ; free virtual = 42329 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7303 ; free virtual = 42329 Phase 9 Depositing Routes Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 7302 ; free virtual = 42327 Phase 1.4 Constrain Clocks/Macros Phase 9 Depositing Routes | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7301 ; free virtual = 42327 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 7337 ; free virtual = 42363 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2140.020 ; gain = 55.477 ; free physical = 7338 ; free virtual = 42363 Writing placer database... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 7312 ; free virtual = 42339 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 7282 ; free virtual = 42310 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 7300 ; free virtual = 42326 Phase 2 Final Placement Cleanup INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 7289 ; free virtual = 42315 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 7234 ; free virtual = 42260 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 7217 ; free virtual = 42243 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:23:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:32 . Memory (MB): peak = 2462.113 ; gain = 340.105 ; free physical = 7087 ; free virtual = 42113 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:23:34 2019... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 498.531 ; free physical = 7097 ; free virtual = 42124 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 498.531 ; free physical = 7108 ; free virtual = 42134 Phase 1 Placer Initialization | Checksum: 208e4f915 INFO: Launching helper process for spawning children vivado processes Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 498.531 ; free physical = 7202 ; free virtual = 42228 Phase 2 Final Placement Cleanup INFO: Helper process launched with PID 29830 Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 498.531 ; free physical = 8076 ; free virtual = 43102 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 498.531 ; free physical = 8027 ; free virtual = 43053 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 8011 ; free virtual = 43038 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' touch build/specimen_010/OK INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29955 Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:23:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2532.875 ; gain = 339.605 ; free physical = 8246 ; free virtual = 43281 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:23:40 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:23:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 2453.871 ; gain = 343.105 ; free physical = 9356 ; free virtual = 44396 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:23:43 2019... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 9423 ; free virtual = 44463 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:23:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2470.148 ; gain = 340.105 ; free physical = 10122 ; free virtual = 45162 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:23:45 2019... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10174 ; free virtual = 45214 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10208 ; free virtual = 45248 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10215 ; free virtual = 45255 --------------------------------------------------------------------------------- Loading site data... INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10611 ; free virtual = 45652 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading route data... Processing options... Creating bitmap... touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 Loading site data... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10870 ; free virtual = 45911 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1 Build RT Design | Checksum: 14c2f3401 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.070 ; gain = 50.668 ; free physical = 10735 ; free virtual = 45777 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14c2f3401 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2144.059 ; gain = 59.656 ; free physical = 10692 ; free virtual = 45735 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14c2f3401 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2144.059 ; gain = 59.656 ; free physical = 10672 ; free virtual = 45714 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] INFO: Launching helper process for spawning children vivado processes WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] INFO: Helper process launched with PID 30213 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10645 ; free virtual = 45687 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10653 ; free virtual = 45695 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10627 ; free virtual = 45669 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10625 ; free virtual = 45667 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10644 ; free virtual = 45686 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10639 ; free virtual = 45681 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10623 ; free virtual = 45665 Phase 4 Rip-up And Reroute | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10621 ; free virtual = 45664 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10619 ; free virtual = 45661 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10617 ; free virtual = 45659 Phase 6 Post Hold Fix | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10615 ; free virtual = 45657 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10593 ; free virtual = 45636 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10590 ; free virtual = 45632 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10560 ; free virtual = 45603 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 10604 ; free virtual = 45646 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:53 . Memory (MB): peak = 2217.777 ; gain = 165.391 ; free physical = 10604 ; free virtual = 45646 Writing placer database... Creating bitstream... Creating bitstream... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.777 ; gain = 0.000 ; free physical = 10387 ; free virtual = 45458 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 10387 ; free virtual = 45457 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 10384 ; free virtual = 45455 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10366 ; free virtual = 45438 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10316 ; free virtual = 45363 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10309 ; free virtual = 45357 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10300 ; free virtual = 45348 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10297 ; free virtual = 45345 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10291 ; free virtual = 45340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10289 ; free virtual = 45338 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10287 ; free virtual = 45335 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10278 ; free virtual = 45327 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 10277 ; free virtual = 45326 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 10832 ; free virtual = 45886 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 10848 ; free virtual = 45901 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10775 ; free virtual = 45829 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30317 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10690 ; free virtual = 45743 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10762 ; free virtual = 45816 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10754 ; free virtual = 45808 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10745 ; free virtual = 45799 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10742 ; free virtual = 45796 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10739 ; free virtual = 45793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10742 ; free virtual = 45796 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10741 ; free virtual = 45795 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10737 ; free virtual = 45791 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 10738 ; free virtual = 45792 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10700 ; free virtual = 45754 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10662 ; free virtual = 45716 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10659 ; free virtual = 45713 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10624 ; free virtual = 45678 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:24:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2475.121 ; gain = 333.105 ; free physical = 10593 ; free virtual = 45647 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:24:02 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:24:03 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:32 . Memory (MB): peak = 2475.125 ; gain = 335.105 ; free physical = 10544 ; free virtual = 45598 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:24:03 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 12365 ; free virtual = 47420 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30404 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 12249 ; free virtual = 47305 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 12267 ; free virtual = 47323 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 12272 ; free virtual = 47328 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } report_drc (run_mandatory_drcs) completed successfully ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. # generate_top Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 12157 ; free virtual = 47213 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 12134 ; free virtual = 47190 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30544 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 11976 ; free virtual = 47032 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 11924 ; free virtual = 46980 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 11912 ; free virtual = 46968 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11904 ; free virtual = 46960 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 11850 ; free virtual = 46906 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11856 ; free virtual = 46912 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11856 ; free virtual = 46913 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: Helper process launched with PID 30584 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11851 ; free virtual = 46908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11851 ; free virtual = 46908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11851 ; free virtual = 46908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11853 ; free virtual = 46909 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11853 ; free virtual = 46910 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11857 ; free virtual = 46913 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 11858 ; free virtual = 46915 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 11808 ; free virtual = 46864 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 11807 ; free virtual = 46864 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 11798 ; free virtual = 46854 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 11614 ; free virtual = 46671 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 11294 ; free virtual = 46351 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 11162 ; free virtual = 46219 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:16] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 11131 ; free virtual = 46188 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 11095 ; free virtual = 46152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 11093 ; free virtual = 46151 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1 Build RT Design | Checksum: 130471fa6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2134.074 ; gain = 49.668 ; free physical = 11093 ; free virtual = 46150 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 11079 ; free virtual = 46136 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Starting Placer Task WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 11071 ; free virtual = 46128 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 11075 ; free virtual = 46132 Loading site data... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 130471fa6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 11049 ; free virtual = 46110 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 130471fa6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 11045 ; free virtual = 46106 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 11011 ; free virtual = 46070 --------------------------------------------------------------------------------- Loading route data... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Processing options... Creating bitmap... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 10950 ; free virtual = 46013 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 10894 ; free virtual = 45958 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10886 ; free virtual = 45950 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 2 Router Initialization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10890 ; free virtual = 45953 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 10897 ; free virtual = 45955 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 10897 ; free virtual = 45955 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 10887 ; free virtual = 45944 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10869 ; free virtual = 45926 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10861 ; free virtual = 45919 Phase 4 Rip-up And Reroute | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10854 ; free virtual = 45912 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10851 ; free virtual = 45908 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10848 ; free virtual = 45906 Phase 6 Post Hold Fix | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10847 ; free virtual = 45905 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10809 ; free virtual = 45866 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10805 ; free virtual = 45862 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10782 ; free virtual = 45840 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 10824 ; free virtual = 45881 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:49 . Memory (MB): peak = 2217.781 ; gain = 165.391 ; free physical = 10823 ; free virtual = 45881 Writing placer database... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10789 ; free virtual = 45849 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10788 ; free virtual = 45848 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10785 ; free virtual = 45846 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10784 ; free virtual = 45845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10784 ; free virtual = 45845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10784 ; free virtual = 45845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10784 ; free virtual = 45845 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 10783 ; free virtual = 45845 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 10784 ; free virtual = 45846 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: 10072c28e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2134.078 ; gain = 49.668 ; free physical = 10637 ; free virtual = 45705 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 10570 ; free virtual = 45641 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 10572 ; free virtual = 45644 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 10548 ; free virtual = 45623 ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 10584 ; free virtual = 45658 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 10524 ; free virtual = 45599 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 10526 ; free virtual = 45602 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 2 Router Initialization | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10461 ; free virtual = 45538 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 10270 ; free virtual = 45349 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10259 ; free virtual = 45338 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10239 ; free virtual = 45318 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4 Rip-up And Reroute | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10225 ; free virtual = 45304 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10212 ; free virtual = 45292 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10202 ; free virtual = 45281 Phase 6 Post Hold Fix | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10193 ; free virtual = 45273 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Timing 38-35] Done setting XDC timing constraints. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10116 ; free virtual = 45197 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10126 ; free virtual = 45207 Phase 9 Depositing Routes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30693 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.449 ; gain = 0.000 ; free physical = 10077 ; free virtual = 45161 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 9 Depositing Routes | Checksum: 1a3bb806c Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10071 ; free virtual = 45155 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.371 ; gain = 95.961 ; free physical = 10114 ; free virtual = 45198 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:52 . Memory (MB): peak = 2219.160 ; gain = 166.766 ; free physical = 10112 ; free virtual = 45196 Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 10110 ; free virtual = 45196 Writing placer database... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9996 ; free virtual = 45087 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9975 ; free virtual = 45067 Phase 1.4 Constrain Clocks/Macros INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30746 Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9970 ; free virtual = 45062 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9995 ; free virtual = 45087 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9986 ; free virtual = 45079 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9985 ; free virtual = 45078 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.492 ; gain = 583.562 ; free physical = 9984 ; free virtual = 45077 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 9981 ; free virtual = 45048 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 9702 ; free virtual = 44773 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1303.691 ; gain = 208.242 ; free physical = 9663 ; free virtual = 44738 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Starting Routing Task --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1303.691 ; gain = 208.242 ; free physical = 9644 ; free virtual = 44719 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 9643 ; free virtual = 44718 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9640 ; free virtual = 44716 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 9613 ; free virtual = 44692 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 9609 ; free virtual = 44690 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9572 ; free virtual = 44650 Phase 1.3 Build Placer Netlist Model No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9580 ; free virtual = 44659 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9579 ; free virtual = 44658 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9572 ; free virtual = 44652 Phase 2 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 9559 ; free virtual = 44640 --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9559 ; free virtual = 44640 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9559 ; free virtual = 44640 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 9558 ; free virtual = 44640 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 9554 ; free virtual = 44636 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9548 ; free virtual = 44632 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9546 ; free virtual = 44631 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9544 ; free virtual = 44628 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9543 ; free virtual = 44627 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9541 ; free virtual = 44626 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9540 ; free virtual = 44625 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9539 ; free virtual = 44624 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9534 ; free virtual = 44619 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.676 ; gain = 216.219 ; free physical = 9552 ; free virtual = 44637 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9541 ; free virtual = 44628 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Creating bitstream... --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2219.160 ; gain = 0.000 ; free physical = 9529 ; free virtual = 44618 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2219.160 ; gain = 0.000 ; free physical = 9507 ; free virtual = 44572 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9457 ; free virtual = 44522 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9452 ; free virtual = 44517 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9430 ; free virtual = 44495 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9432 ; free virtual = 44496 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9418 ; free virtual = 44482 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9382 ; free virtual = 44447 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9370 ; free virtual = 44434 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9355 ; free virtual = 44420 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.590 ; gain = 269.961 ; free physical = 9359 ; free virtual = 44423 INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 9369 ; free virtual = 44437 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 9577 ; free virtual = 44646 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9569 ; free virtual = 44637 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9499 ; free virtual = 44568 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9500 ; free virtual = 44569 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9502 ; free virtual = 44570 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9501 ; free virtual = 44570 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9501 ; free virtual = 44569 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9500 ; free virtual = 44568 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9499 ; free virtual = 44567 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9497 ; free virtual = 44565 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 9497 ; free virtual = 44565 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 9480 ; free virtual = 44548 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.434 ; gain = 54.992 ; free physical = 9472 ; free virtual = 44540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 9353 ; free virtual = 44422 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 9342 ; free virtual = 44410 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 9342 ; free virtual = 44410 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 9143 ; free virtual = 44212 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 9145 ; free virtual = 44214 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 9138 ; free virtual = 44207 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:24:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Device 21-403] Loading part xc7z020clg400-1 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:42 . Memory (MB): peak = 2607.938 ; gain = 390.160 ; free physical = 9122 ; free virtual = 44191 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:24:40 2019... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.949 ; gain = 115.508 ; free physical = 9070 ; free virtual = 44137 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2719] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2737] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2776] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2802] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2820] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2859] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2885] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2903] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2942] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2968] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2986] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3025] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3051] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3069] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3108] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3134] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3152] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3191] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3217] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3235] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3274] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3300] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3318] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3357] INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4563] Bitstream size: 4243411 bytes WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7136] Config size: 1060815 words WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7717] Number of configuration frames: 9996 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. DONE WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 Loading data files... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9748 ; free virtual = 44817 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9715 ; free virtual = 44784 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9714 ; free virtual = 44784 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 9680 ; free virtual = 44749 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9594 ; free virtual = 44663 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9644 ; free virtual = 44719 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9640 ; free virtual = 44715 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9627 ; free virtual = 44702 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9612 ; free virtual = 44687 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9597 ; free virtual = 44672 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 9584 ; free virtual = 44659 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 9583 ; free virtual = 44658 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 9505 ; free virtual = 44580 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 9404 ; free virtual = 44478 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 9400 ; free virtual = 44475 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.254 ; gain = 384.359 ; free physical = 9417 ; free virtual = 44492 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1551.957 ; gain = 0.000 ; free physical = 9251 ; free virtual = 44325 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1551.957 ; gain = 0.000 ; free physical = 9212 ; free virtual = 44287 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 9141 ; free virtual = 44216 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 9123 ; free virtual = 44197 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9119 ; free virtual = 44194 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8980 ; free virtual = 44054 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8979 ; free virtual = 44053 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8976 ; free virtual = 44051 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8976 ; free virtual = 44051 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8974 ; free virtual = 44049 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8974 ; free virtual = 44049 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8972 ; free virtual = 44046 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8966 ; free virtual = 44041 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 8966 ; free virtual = 44041 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8840 ; free virtual = 43915 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8750 ; free virtual = 43825 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8697 ; free virtual = 43772 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 8422 ; free virtual = 43497 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Processing options... Creating bitmap... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8380 ; free virtual = 43454 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8375 ; free virtual = 43450 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8375 ; free virtual = 43450 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8375 ; free virtual = 43449 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8374 ; free virtual = 43449 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8374 ; free virtual = 43449 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8373 ; free virtual = 43448 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8373 ; free virtual = 43448 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8373 ; free virtual = 43448 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8372 ; free virtual = 43447 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8371 ; free virtual = 43446 Phase 2 Final Placement Cleanup Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8371 ; free virtual = 43445 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 8363 ; free virtual = 43438 Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8363 ; free virtual = 43438 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Project 1-571] Translating synthesized netlist Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8350 ; free virtual = 43425 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 8350 ; free virtual = 43425 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 7773 ; free virtual = 42848 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1424.930 ; gain = 342.047 ; free physical = 7775 ; free virtual = 42850 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 7738 ; free virtual = 42812 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14eeb77a5 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 7731 ; free virtual = 42806 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 7686 ; free virtual = 42760 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 7685 ; free virtual = 42760 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 7684 ; free virtual = 42759 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 7684 ; free virtual = 42759 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 7683 ; free virtual = 42757 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 7684 ; free virtual = 42759 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 7684 ; free virtual = 42759 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:39 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 7529 ; free virtual = 42604 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 7465 ; free virtual = 42539 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 7464 ; free virtual = 42539 Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... INFO: Launching helper process for spawning children vivado processes INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: Helper process launched with PID 31222 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 7199 ; free virtual = 42278 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7063 ; free virtual = 42142 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7028 ; free virtual = 42107 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7026 ; free virtual = 42105 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7040 ; free virtual = 42119 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7025 ; free virtual = 42104 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7021 ; free virtual = 42100 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 7021 ; free virtual = 42100 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 6960 ; free virtual = 42039 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:25:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:48 . Memory (MB): peak = 2608.402 ; gain = 390.621 ; free physical = 7007 ; free virtual = 42091 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:25:15 2019... Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Bitstream size: 4243411 bytes Config size: 1060815 words Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.160 ; gain = 451.203 ; free physical = 8330 ; free virtual = 43412 Phase 1.3 Build Placer Netlist Model Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.160 ; gain = 451.203 ; free physical = 8244 ; free virtual = 43332 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.160 ; gain = 451.203 ; free physical = 8210 ; free virtual = 43298 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.160 ; gain = 451.203 ; free physical = 8207 ; free virtual = 43295 Phase 2 Global Placement Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.176 ; gain = 44.668 ; free physical = 8167 ; free virtual = 43255 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.164 ; gain = 50.656 ; free physical = 8094 ; free virtual = 43183 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.164 ; gain = 50.656 ; free physical = 8084 ; free virtual = 43172 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:25:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:47 . Memory (MB): peak = 2609.320 ; gain = 390.160 ; free physical = 8086 ; free virtual = 43174 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:25:20 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.469 ; gain = 61.961 ; free physical = 8225 ; free virtual = 43312 Phase 3 Initial Routing Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.469 ; gain = 63.961 ; free physical = 9141 ; free virtual = 44228 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.469 ; gain = 63.961 ; free physical = 9141 ; free virtual = 44228 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.469 ; gain = 63.961 ; free physical = 9141 ; free virtual = 44228 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.469 ; gain = 63.961 ; free physical = 9140 ; free virtual = 44227 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.469 ; gain = 63.961 ; free physical = 9140 ; free virtual = 44227 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2086.469 ; gain = 63.961 ; free physical = 9140 ; free virtual = 44227 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2086.469 ; gain = 63.961 ; free physical = 9124 ; free virtual = 44211 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.469 ; gain = 66.961 ; free physical = 9124 ; free virtual = 44212 Phase 9 Depositing Routes touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.469 ; gain = 66.961 ; free physical = 9135 ; free virtual = 44223 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.469 ; gain = 66.961 ; free physical = 9173 ; free virtual = 44261 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2128.258 ; gain = 137.766 ; free physical = 9172 ; free virtual = 44260 Writing placer database... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Writing XDEF routing. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 9101 ; free virtual = 44191 Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 9095 ; free virtual = 44187 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 9063 ; free virtual = 44154 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 9058 ; free virtual = 44149 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 8771 ; free virtual = 43859 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 8724 ; free virtual = 43812 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 8736 ; free virtual = 43825 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 8747 ; free virtual = 43836 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 8752 ; free virtual = 43841 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 8752 ; free virtual = 43841 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 8753 ; free virtual = 43841 Phase 2 Global Placement | Checksum: 18079d4e9 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 8757 ; free virtual = 43846 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8760 ; free virtual = 43849 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 7 Route finalize Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.449 ; gain = 0.000 ; free physical = 8782 ; free virtual = 43871 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Running DRC as a precondition to command write_bitstream Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.590 ; gain = 62.086 ; free physical = 8745 ; free virtual = 43834 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2087.590 ; gain = 64.086 ; free physical = 8742 ; free virtual = 43831 Phase 9 Depositing Routes Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8736 ; free virtual = 43825 Phase 3.2 Commit Most Macros & LUTRAMs Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2087.590 ; gain = 64.086 ; free physical = 8754 ; free virtual = 43842 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2087.590 ; gain = 64.086 ; free physical = 8787 ; free virtual = 43876 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2126.379 ; gain = 134.891 ; free physical = 8785 ; free virtual = 43874 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2126.379 ; gain = 0.000 ; free physical = 8754 ; free virtual = 43846 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8797 ; free virtual = 43887 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 104554cdc Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 8796 ; free virtual = 43885 Phase 1.3 Build Placer Netlist Model Phase 3.3 Area Swap Optimization Phase 1.3 Build Placer Netlist Model | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 8787 ; free virtual = 43876 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 8784 ; free virtual = 43873 Phase 1 Placer Initialization | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 8780 ; free virtual = 43870 Phase 2 Global Placement Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8765 ; free virtual = 43855 Phase 3.4 Pipeline Register Optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Time (s): cpu = 00:00:29 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8788 ; free virtual = 43878 Phase 3.5 Small Shape Detail Placement Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8415 ; free virtual = 43504 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8383 ; free virtual = 43472 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8364 ; free virtual = 43454 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8355 ; free virtual = 43445 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8338 ; free virtual = 43428 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.234 ; gain = 0.000 ; free physical = 8334 ; free virtual = 43423 Phase 4.2 Post Placement Cleanup Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Global Placement | Checksum: 19390bb85 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8336 ; free virtual = 43425 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19390bb85 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8328 ; free virtual = 43418 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22760be29 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8325 ; free virtual = 43414 Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8318 ; free virtual = 43408 Phase 3.3 Area Swap Optimization Phase 4.3 Placer Reporting Phase 3.3 Area Swap Optimization | Checksum: 2013b9bf4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8329 ; free virtual = 43418 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1caeffc59 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8334 ; free virtual = 43424 Phase 3.5 Small Shape Detail Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 8357 ; free virtual = 43446 Phase 1.3 Build Placer Netlist Model Loading data files... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8352 ; free virtual = 43442 Phase 4.4 Final Placement Cleanup Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 8350 ; free virtual = 43439 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 8342 ; free virtual = 43431 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 8335 ; free virtual = 43425 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 8334 ; free virtual = 43423 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 8327 ; free virtual = 43416 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 576.562 ; free physical = 8326 ; free virtual = 43416 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8291 ; free virtual = 43381 Phase 3.6 Re-assign LUT pins Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8291 ; free virtual = 43380 Phase 3.6 Re-assign LUT pins | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8293 ; free virtual = 43382 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8298 ; free virtual = 43387 Phase 3 Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8305 ; free virtual = 43394 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8306 ; free virtual = 43395 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8305 ; free virtual = 43394 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8304 ; free virtual = 43394 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8302 ; free virtual = 43392 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8304 ; free virtual = 43394 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8304 ; free virtual = 43393 Ending Placer Task | Checksum: 1d105b369 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 8340 ; free virtual = 43430 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 2084.535 ; gain = 659.605 ; free physical = 8340 ; free virtual = 43430 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.207 ; gain = 547.250 ; free physical = 8300 ; free virtual = 43390 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.207 ; gain = 631.953 ; free physical = 8299 ; free virtual = 43388 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading data files... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec660a5f ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.172 ; gain = 44.668 ; free physical = 8030 ; free virtual = 43120 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2074.160 ; gain = 50.656 ; free physical = 7991 ; free virtual = 43081 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2074.160 ; gain = 50.656 ; free physical = 7990 ; free virtual = 43080 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2086.590 ; gain = 63.086 ; free physical = 7944 ; free virtual = 43034 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.590 ; gain = 63.086 ; free physical = 7920 ; free virtual = 43010 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.590 ; gain = 63.086 ; free physical = 7918 ; free virtual = 43008 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.590 ; gain = 63.086 ; free physical = 7918 ; free virtual = 43007 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.590 ; gain = 63.086 ; free physical = 7918 ; free virtual = 43007 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.590 ; gain = 63.086 ; free physical = 7917 ; free virtual = 43006 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.590 ; gain = 63.086 ; free physical = 7907 ; free virtual = 42996 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.590 ; gain = 63.086 ; free physical = 7890 ; free virtual = 42979 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.590 ; gain = 65.086 ; free physical = 7889 ; free virtual = 42978 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.590 ; gain = 65.086 ; free physical = 7885 ; free virtual = 42975 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.590 ; gain = 65.086 ; free physical = 7924 ; free virtual = 43013 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2127.379 ; gain = 135.891 ; free physical = 7924 ; free virtual = 43013 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2127.379 ; gain = 0.000 ; free physical = 7913 ; free virtual = 43006 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 7107 ; free virtual = 42199 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 568 Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 6925 ; free virtual = 42017 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 6948 ; free virtual = 42040 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2062.930 ; gain = 43.668 ; free physical = 6816 ; free virtual = 41908 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2067.918 ; gain = 48.656 ; free physical = 6783 ; free virtual = 41875 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2067.918 ; gain = 48.656 ; free physical = 6783 ; free virtual = 41875 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2078.973 ; gain = 59.711 ; free physical = 6747 ; free virtual = 41839 Phase 3 Initial Routing INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 621 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 6729 ; free virtual = 41821 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 6726 ; free virtual = 41818 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 6725 ; free virtual = 41818 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 6725 ; free virtual = 41817 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 6725 ; free virtual = 41817 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 6725 ; free virtual = 41817 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2081.973 ; gain = 62.711 ; free physical = 6698 ; free virtual = 41791 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2083.973 ; gain = 64.711 ; free physical = 6695 ; free virtual = 41787 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2083.973 ; gain = 64.711 ; free physical = 6700 ; free virtual = 41792 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2083.973 ; gain = 64.711 ; free physical = 6737 ; free virtual = 41829 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2122.762 ; gain = 135.516 ; free physical = 6737 ; free virtual = 41829 Creating bitstream... Writing placer database... Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2122.762 ; gain = 0.000 ; free physical = 6726 ; free virtual = 41823 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 6953 ; free virtual = 42050 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 97328c80 Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2057.938 ; gain = 93.668 ; free physical = 6871 ; free virtual = 41969 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 97328c80 Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2063.926 ; gain = 99.656 ; free physical = 6833 ; free virtual = 41933 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 97328c80 Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2063.926 ; gain = 99.656 ; free physical = 6833 ; free virtual = 41933 Loading site data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1088853dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 6892 ; free virtual = 41993 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7064 ; free virtual = 42165 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7059 ; free virtual = 42160 Phase 4 Rip-up And Reroute | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7063 ; free virtual = 42164 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7063 ; free virtual = 42164 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7063 ; free virtual = 42164 Phase 6 Post Hold Fix | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7063 ; free virtual = 42164 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:25:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2462.434 ; gain = 334.176 ; free physical = 7023 ; free virtual = 42124 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7018 ; free virtual = 42118 Phase 8 Verifying routed nets INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:25:51 2019... Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 7017 ; free virtual = 42118 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 7017 ; free virtual = 42118 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 7050 ; free virtual = 42150 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2111.770 ; gain = 179.516 ; free physical = 7049 ; free virtual = 42150 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2111.770 ; gain = 0.000 ; free physical = 7074 ; free virtual = 42176 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 7899 ; free virtual = 43000 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Loading data files... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 7900 ; free virtual = 43001 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:25:54 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2462.555 ; gain = 336.176 ; free physical = 7927 ; free virtual = 43029 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:25:54 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8026 ; free virtual = 43127 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8680 ; free virtual = 43782 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 8680 ; free virtual = 43782 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8955 ; free virtual = 44067 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8952 ; free virtual = 44063 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8934 ; free virtual = 44045 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8920 ; free virtual = 44031 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8930 ; free virtual = 44042 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8936 ; free virtual = 44047 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8941 ; free virtual = 44052 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8950 ; free virtual = 44061 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 8953 ; free virtual = 44065 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8965 ; free virtual = 44076 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8942 ; free virtual = 44053 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8941 ; free virtual = 44052 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8937 ; free virtual = 44048 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.957 ; gain = 43.668 ; free physical = 8771 ; free virtual = 43883 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.945 ; gain = 49.656 ; free physical = 8736 ; free virtual = 43848 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.945 ; gain = 49.656 ; free physical = 8737 ; free virtual = 43848 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:26:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2462.555 ; gain = 335.176 ; free physical = 8743 ; free virtual = 43855 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:26:00 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10276a5af Bitstream size: 4243411 bytes Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 9691 ; free virtual = 44802 Phase 3 Initial Routing Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 9665 ; free virtual = 44777 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 9665 ; free virtual = 44776 Phase 4 Rip-up And Reroute | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 9665 ; free virtual = 44776 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 9665 ; free virtual = 44776 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 9665 ; free virtual = 44776 Phase 6 Post Hold Fix | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 9665 ; free virtual = 44776 touch build/specimen_015/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 9669 ; free virtual = 44780 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2093.250 ; gain = 67.961 ; free physical = 9669 ; free virtual = 44781 Phase 9 Depositing Routes Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 15 #of bits: 12552 #of tags: 110 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 Phase 9 Depositing Routes | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2093.250 ; gain = 67.961 ; free physical = 9669 ; free virtual = 44780 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2093.250 ; gain = 67.961 ; free physical = 9707 ; free virtual = 44818 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2132.039 ; gain = 138.766 ; free physical = 9707 ; free virtual = 44818 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2132.039 ; gain = 0.000 ; free physical = 9640 ; free virtual = 44755 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9169 ; free virtual = 44283 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9152 ; free virtual = 44265 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9162 ; free virtual = 44276 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9156 ; free virtual = 44289 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9155 ; free virtual = 44288 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9154 ; free virtual = 44287 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9153 ; free virtual = 44286 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9151 ; free virtual = 44284 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9150 ; free virtual = 44283 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9149 ; free virtual = 44282 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9144 ; free virtual = 44278 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 9141 ; free virtual = 44275 INFO: [Project 1-571] Translating synthesized netlist Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 9056 ; free virtual = 44172 --------------------------------------------------------------------------------- Loading data files... INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8978 ; free virtual = 44093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 8978 ; free virtual = 44094 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 8776 ; free virtual = 43891 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Writing bitstream ./design.bit... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 1c3aa3009 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 9344 ; free virtual = 44467 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1c3aa3009 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 9277 ; free virtual = 44401 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1c3aa3009 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 9276 ; free virtual = 44399 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 9238 ; free virtual = 44361 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 9237 ; free virtual = 44360 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 171fe028c Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9178 ; free virtual = 44302 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9215 ; free virtual = 44338 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 9217 ; free virtual = 44340 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9212 ; free virtual = 44336 Phase 4 Rip-up And Reroute | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9212 ; free virtual = 44335 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9213 ; free virtual = 44336 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9213 ; free virtual = 44336 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Phase 6 Post Hold Fix | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9213 ; free virtual = 44336 Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9176 ; free virtual = 44299 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9175 ; free virtual = 44298 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d35d7ab Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9190 ; free virtual = 44313 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2130.105 ; gain = 30.898 ; free physical = 9222 ; free virtual = 44345 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9224 ; free virtual = 44347 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2141.012 ; gain = 56.477 ; free physical = 9223 ; free virtual = 44346 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1095 Phase 2.1 Fix Topology Constraints Phase 1 Build RT Design | Checksum: 18d0b5f55 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.961 ; gain = 42.668 ; free physical = 9192 ; free virtual = 44315 Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2136.094 ; gain = 36.887 ; free physical = 9191 ; free virtual = 44314 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2136.094 ; gain = 36.887 ; free physical = 9191 ; free virtual = 44314 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing placer database... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18d0b5f55 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.949 ; gain = 48.656 ; free physical = 9156 ; free virtual = 44280 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18d0b5f55 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.949 ; gain = 48.656 ; free physical = 9155 ; free virtual = 44279 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2141.012 ; gain = 0.000 ; free physical = 9142 ; free virtual = 44268 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9041 ; free virtual = 44165 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.254 ; gain = 61.961 ; free physical = 9031 ; free virtual = 44155 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9062 ; free virtual = 44186 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9061 ; free virtual = 44185 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9062 ; free virtual = 44186 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9062 ; free virtual = 44186 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9062 ; free virtual = 44186 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9062 ; free virtual = 44186 Running DRC as a precondition to command write_bitstream Phase 7 Route finalize Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 9057 ; free virtual = 44181 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 9051 ; free virtual = 44175 Phase 4 Rip-up And Reroute | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 9048 ; free virtual = 44172 Phase 5 Delay and Skew Optimization Congestion Report North Dir 1x1 Area, Max Cong = Phase 5 Delay and Skew Optimization | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 9048 ; free virtual = 44172 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 6.1 Hold Fix Iter | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 9048 ; free virtual = 44172 Phase 6 Post Hold Fix | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 9047 ; free virtual = 44171 Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9045 ; free virtual = 44169 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9043 ; free virtual = 44167 Phase 9 Depositing Routes Phase 7 Route finalize Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9039 ; free virtual = 44163 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.148 ; gain = 55.941 ; free physical = 9072 ; free virtual = 44196 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2193.938 ; gain = 94.730 ; free physical = 9074 ; free virtual = 44198 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18932909f Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 9066 ; free virtual = 44190 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18932909f Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 9062 ; free virtual = 44187 Phase 9 Depositing Routes Writing placer database... Phase 9 Depositing Routes | Checksum: 18932909f Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 9047 ; free virtual = 44172 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.254 ; gain = 65.961 ; free physical = 9079 ; free virtual = 44204 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.043 ; gain = 136.766 ; free physical = 9080 ; free virtual = 44204 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:26:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.875 ; gain = 342.105 ; free physical = 9048 ; free virtual = 44176 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:26:18 2019... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:26:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Write XDEF Complete: Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.40 . Memory (MB): peak = 2130.043 ; gain = 0.000 ; free physical = 9043 ; free virtual = 44174 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2461.867 ; gain = 339.105 ; free physical = 9052 ; free virtual = 44183 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:26:18 2019... Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading route data... touch build/specimen_012/OK Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Processing options... Creating bitmap... touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 1339.102 ; gain = 243.184 ; free physical = 10731 ; free virtual = 45872 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1339.102 ; gain = 243.184 ; free physical = 10674 ; free virtual = 45818 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1251 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.938 ; gain = 0.000 ; free physical = 10650 ; free virtual = 45804 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10654 ; free virtual = 45808 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.938 ; gain = 0.000 ; free physical = 10675 ; free virtual = 45807 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:14 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 10580 ; free virtual = 45712 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Running DRC as a precondition to command write_bitstream INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10585 ; free virtual = 45717 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10574 ; free virtual = 45705 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10457 ; free virtual = 45589 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10445 ; free virtual = 45577 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10455 ; free virtual = 45587 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10433 ; free virtual = 45565 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10435 ; free virtual = 45566 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1347.078 ; gain = 251.160 ; free physical = 10425 ; free virtual = 45557 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1347.086 ; gain = 251.160 ; free physical = 10426 ; free virtual = 45558 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1393 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10379 ; free virtual = 45511 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1545.859 ; gain = 0.000 ; free physical = 10350 ; free virtual = 45481 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.64 . Memory (MB): peak = 1545.859 ; gain = 0.000 ; free physical = 10326 ; free virtual = 45457 Creating bitstream... INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10178 ; free virtual = 45310 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10185 ; free virtual = 45317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10185 ; free virtual = 45317 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10169 ; free virtual = 45301 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 10139 ; free virtual = 45275 --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.434 ; gain = 60.824 ; free physical = 9342 ; free virtual = 44478 --------------------------------------------------------------------------------- Loading site data... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 9280 ; free virtual = 44417 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:26:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.145 ; gain = 338.105 ; free physical = 9223 ; free virtual = 44360 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:26:35 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10109 ; free virtual = 45246 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10107 ; free virtual = 45243 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10107 ; free virtual = 45243 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10110 ; free virtual = 45247 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10110 ; free virtual = 45246 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10109 ; free virtual = 45246 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 10109 ; free virtual = 45246 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.684 ; gain = 210.242 ; free physical = 9958 ; free virtual = 45096 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.684 ; gain = 210.242 ; free physical = 10015 ; free virtual = 45153 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 10012 ; free virtual = 45150 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 9941 ; free virtual = 45078 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 9940 ; free virtual = 45077 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 9939 ; free virtual = 45077 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 9939 ; free virtual = 45077 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 9939 ; free virtual = 45076 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 9939 ; free virtual = 45076 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 9938 ; free virtual = 45076 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.660 ; gain = 218.219 ; free physical = 9938 ; free virtual = 45075 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.668 ; gain = 218.219 ; free physical = 9939 ; free virtual = 45077 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] Creating bitstream... Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.941 ; gain = 132.332 ; free physical = 9862 ; free virtual = 45000 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.941 ; gain = 132.332 ; free physical = 9820 ; free virtual = 44958 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.969 ; gain = 140.359 ; free physical = 9819 ; free virtual = 44957 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1563 Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1268.086 ; gain = 172.477 ; free physical = 9788 ; free virtual = 44931 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: Helper process launched with PID 1610 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 1397.676 ; gain = 314.789 ; free physical = 9788 ; free virtual = 44931 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Writing bitstream ./design.bit... INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.707 ; gain = 0.000 ; free physical = 9723 ; free virtual = 44870 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1461.707 ; gain = 0.000 ; free physical = 9723 ; free virtual = 44869 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 1476.844 ; gain = 393.953 ; free physical = 9960 ; free virtual = 45111 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 9984 ; free virtual = 45135 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:26:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 2475.117 ; gain = 334.105 ; free physical = 10021 ; free virtual = 45174 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:26:50 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 10932 ; free virtual = 46085 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.680 ; gain = 249.070 ; free physical = 10974 ; free virtual = 46146 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Starting Placer Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.391 ; gain = 506.531 ; free physical = 10963 ; free virtual = 46135 Phase 1.3 Build Placer Netlist Model INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.680 ; gain = 249.070 ; free physical = 10960 ; free virtual = 46133 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:26:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.148 ; gain = 340.105 ; free physical = 10947 ; free virtual = 46119 Phase 1 Placer Initialization INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:26:52 2019... Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1556.875 ; gain = 0.000 ; free physical = 11000 ; free virtual = 46172 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1556.875 ; gain = 0.000 ; free physical = 11022 ; free virtual = 46195 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 11945 ; free virtual = 47098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 11945 ; free virtual = 47098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 11944 ; free virtual = 47097 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Config size: 1060815 words --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:26:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.543 ; gain = 338.605 ; free physical = 11872 ; free virtual = 47027 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:26:53 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 12815 ; free virtual = 47969 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 12802 ; free virtual = 47956 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 12849 ; free virtual = 48003 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 12847 ; free virtual = 48001 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 12838 ; free virtual = 47993 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 12838 ; free virtual = 47992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 12836 ; free virtual = 47990 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.703 ; gain = 270.094 ; free physical = 12831 ; free virtual = 47985 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.711 ; gain = 270.094 ; free physical = 12833 ; free virtual = 47987 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 12825 ; free virtual = 47979 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 506.531 ; free physical = 12723 ; free virtual = 47880 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 12719 ; free virtual = 47878 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 12757 ; free virtual = 47913 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 506.531 ; free physical = 12756 ; free virtual = 47916 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 12750 ; free virtual = 47906 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 12749 ; free virtual = 47905 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 506.531 ; free physical = 12743 ; free virtual = 47899 Phase 2 Final Placement Cleanup INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 12742 ; free virtual = 47897 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 506.531 ; free physical = 12719 ; free virtual = 47875 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 506.531 ; free physical = 12700 ; free virtual = 47856 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 12691 ; free virtual = 47847 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 12618 ; free virtual = 47780 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 12359 ; free virtual = 47514 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 12317 ; free virtual = 47473 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12194 ; free virtual = 47350 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1943 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 12083 ; free virtual = 47239 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 12109 ; free virtual = 47264 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 12095 ; free virtual = 47250 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.375 ; gain = 384.492 ; free physical = 12137 ; free virtual = 47293 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12109 ; free virtual = 47265 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 12100 ; free virtual = 47256 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11972 ; free virtual = 47128 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11972 ; free virtual = 47128 --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11958 ; free virtual = 47114 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11991 ; free virtual = 47147 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11991 ; free virtual = 47146 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11987 ; free virtual = 47143 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11985 ; free virtual = 47141 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11980 ; free virtual = 47136 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 11966 ; free virtual = 47122 --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11983 ; free virtual = 47139 --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11996 ; free virtual = 47151 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11980 ; free virtual = 47136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11957 ; free virtual = 47113 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11942 ; free virtual = 47097 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:38 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11925 ; free virtual = 47081 Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 11924 ; free virtual = 47080 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1548.078 ; gain = 0.000 ; free physical = 11745 ; free virtual = 46901 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.55 . Memory (MB): peak = 1548.078 ; gain = 0.000 ; free physical = 11727 ; free virtual = 46883 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.195 ; gain = 0.000 ; free physical = 11556 ; free virtual = 46712 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.238 ; gain = 470.531 ; free physical = 11385 ; free virtual = 46540 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.238 ; gain = 470.531 ; free physical = 11380 ; free virtual = 46536 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.238 ; gain = 470.531 ; free physical = 11379 ; free virtual = 46535 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.238 ; gain = 470.531 ; free physical = 11378 ; free virtual = 46534 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.238 ; gain = 470.531 ; free physical = 11380 ; free virtual = 46535 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.238 ; gain = 470.531 ; free physical = 11380 ; free virtual = 46536 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.238 ; gain = 534.562 ; free physical = 11380 ; free virtual = 46536 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.363 ; gain = 0.000 ; free physical = 11044 ; free virtual = 46212 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 11015 ; free virtual = 46191 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11008 ; free virtual = 46165 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 10957 ; free virtual = 46135 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 10946 ; free virtual = 46123 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 10941 ; free virtual = 46119 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2084 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 10926 ; free virtual = 46084 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 10925 ; free virtual = 46083 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.406 ; gain = 495.531 ; free physical = 10915 ; free virtual = 46073 Phase 1.3 Build Placer Netlist Model INFO: [Device 21-403] Loading part xc7z020clg400-1 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 10799 ; free virtual = 45957 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 10776 ; free virtual = 45934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 10775 ; free virtual = 45933 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 10766 ; free virtual = 45924 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2132 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2177 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.406 ; gain = 495.531 ; free physical = 10407 ; free virtual = 45565 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.406 ; gain = 495.531 ; free physical = 10400 ; free virtual = 45558 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.406 ; gain = 495.531 ; free physical = 10386 ; free virtual = 45544 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.406 ; gain = 495.531 ; free physical = 10382 ; free virtual = 45540 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.406 ; gain = 495.531 ; free physical = 10396 ; free virtual = 45554 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 1336.070 ; gain = 240.152 ; free physical = 10403 ; free virtual = 45561 --------------------------------------------------------------------------------- 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.406 ; gain = 575.562 ; free physical = 10401 ; free virtual = 45559 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2055.934 ; gain = 91.668 ; free physical = 10270 ; free virtual = 45428 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 10236 ; free virtual = 45395 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 10236 ; free virtual = 45394 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6c93b630 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 10207 ; free virtual = 45366 Phase 3 Initial Routing Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6c93b630 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10170 ; free virtual = 45328 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10169 ; free virtual = 45327 Phase 4 Rip-up And Reroute | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10169 ; free virtual = 45327 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10169 ; free virtual = 45327 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10169 ; free virtual = 45327 Phase 6 Post Hold Fix | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10169 ; free virtual = 45327 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10138 ; free virtual = 45296 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 10135 ; free virtual = 45293 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 10135 ; free virtual = 45293 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 10167 ; free virtual = 45325 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 10167 ; free virtual = 45325 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 10160 ; free virtual = 45320 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1344.102 ; gain = 248.184 ; free physical = 10157 ; free virtual = 45317 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1344.102 ; gain = 248.184 ; free physical = 10105 ; free virtual = 45263 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 10090 ; free virtual = 45248 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1303.680 ; gain = 208.242 ; free physical = 10002 ; free virtual = 45161 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1303.680 ; gain = 208.242 ; free physical = 9986 ; free virtual = 45144 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9981 ; free virtual = 45139 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9959 ; free virtual = 45117 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9903 ; free virtual = 45061 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9903 ; free virtual = 45061 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9901 ; free virtual = 45059 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9900 ; free virtual = 45059 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9898 ; free virtual = 45056 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9895 ; free virtual = 45054 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9893 ; free virtual = 45052 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 9885 ; free virtual = 45044 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9879 ; free virtual = 45037 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 9643 ; free virtual = 44801 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 9680 ; free virtual = 44839 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9746 ; free virtual = 44907 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 9733 ; free virtual = 44892 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 9731 ; free virtual = 44890 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9727 ; free virtual = 44886 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9665 ; free virtual = 44824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9656 ; free virtual = 44815 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 9658 ; free virtual = 44817 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9664 ; free virtual = 44822 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9656 ; free virtual = 44815 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9654 ; free virtual = 44813 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9652 ; free virtual = 44811 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.086 ; gain = 256.160 ; free physical = 9653 ; free virtual = 44811 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-570] Preparing netlist for logic optimization Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.566 ; gain = 0.000 ; free physical = 9592 ; free virtual = 44751 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 9544 ; free virtual = 44703 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7385] Loading data files... WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.281 ; gain = 455.203 ; free physical = 9420 ; free virtual = 44578 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9385 ; free virtual = 44544 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9324 ; free virtual = 44484 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9320 ; free virtual = 44479 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 9266 ; free virtual = 44426 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9268 ; free virtual = 44428 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9229 ; free virtual = 44389 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9169 ; free virtual = 44329 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9163 ; free virtual = 44323 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Device 21-403] Loading part xc7z020clg400-1 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.680 ; gain = 314.797 ; free physical = 9169 ; free virtual = 44328 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9053 ; free virtual = 44213 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.711 ; gain = 0.000 ; free physical = 8850 ; free virtual = 44010 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1463.711 ; gain = 0.000 ; free physical = 8849 ; free virtual = 44009 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a INFO: [Timing 38-35] Done setting XDC timing constraints. Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.281 ; gain = 455.203 ; free physical = 8777 ; free virtual = 43937 Phase 1.4 Constrain Clocks/Macros Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1549.863 ; gain = 0.000 ; free physical = 8775 ; free virtual = 43935 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.195 ; gain = 0.000 ; free physical = 8772 ; free virtual = 43932 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.54 . Memory (MB): peak = 1549.863 ; gain = 0.000 ; free physical = 8771 ; free virtual = 43931 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.281 ; gain = 455.203 ; free physical = 8770 ; free virtual = 43930 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 8749 ; free virtual = 43908 Phase 1.3 Build Placer Netlist Model Phase 1 Placer Initialization | Checksum: 188a0da2a Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 8747 ; free virtual = 43907 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.281 ; gain = 455.203 ; free physical = 8747 ; free virtual = 43907 Phase 1.4 Constrain Clocks/Macros Phase 2 Global Placement Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 8745 ; free virtual = 43905 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 8744 ; free virtual = 43904 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 8743 ; free virtual = 43902 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 8743 ; free virtual = 43903 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.238 ; gain = 580.562 ; free physical = 8743 ; free virtual = 43902 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 8606 ; free virtual = 43765 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 8552 ; free virtual = 43712 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8541 ; free virtual = 43700 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8406 ; free virtual = 43566 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8368 ; free virtual = 43528 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8365 ; free virtual = 43525 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8365 ; free virtual = 43525 Phase 3.2 Commit Most Macros & LUTRAMs --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8364 ; free virtual = 43524 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8364 ; free virtual = 43523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8363 ; free virtual = 43522 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8363 ; free virtual = 43522 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8361 ; free virtual = 43521 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8357 ; free virtual = 43517 Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8354 ; free virtual = 43514 INFO: [Project 1-571] Translating synthesized netlist Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8305 ; free virtual = 43465 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8265 ; free virtual = 43424 Phase 3.4 Pipeline Register Optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8243 ; free virtual = 43402 Phase 3.5 Small Shape Detail Placement No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8220 ; free virtual = 43380 --------------------------------------------------------------------------------- Loading site data... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8197 ; free virtual = 43357 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8185 ; free virtual = 43345 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.574 ; gain = 216.121 ; free physical = 8142 ; free virtual = 43302 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2133.074 ; gain = 48.668 ; free physical = 8136 ; free virtual = 43296 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8134 ; free virtual = 43294 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8132 ; free virtual = 43292 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8131 ; free virtual = 43291 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8131 ; free virtual = 43290 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8130 ; free virtual = 43290 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8130 ; free virtual = 43290 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8130 ; free virtual = 43290 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8129 ; free virtual = 43289 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 8130 ; free virtual = 43290 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8129 ; free virtual = 43289 Phase 3.6 Re-assign LUT pins INFO: [Project 1-571] Translating synthesized netlist Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.574 ; gain = 216.121 ; free physical = 8111 ; free virtual = 43271 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8077 ; free virtual = 43237 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8076 ; free virtual = 43236 Phase 3.7 Pipeline Register Optimization Phase 2.1 Fix Topology Constraints | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2143.062 ; gain = 58.656 ; free physical = 8072 ; free virtual = 43232 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2143.062 ; gain = 58.656 ; free physical = 8071 ; free virtual = 43230 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8065 ; free virtual = 43225 Creating bitstream... Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8061 ; free virtual = 43221 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8054 ; free virtual = 43214 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8044 ; free virtual = 43204 Phase 4.3 Placer Reporting Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8042 ; free virtual = 43202 Phase 3 Initial Routing Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8044 ; free virtual = 43204 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8076 ; free virtual = 43236 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8079 ; free virtual = 43239 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8078 ; free virtual = 43238 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8078 ; free virtual = 43238 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8078 ; free virtual = 43238 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8078 ; free virtual = 43238 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8078 ; free virtual = 43238 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 8077 ; free virtual = 43237 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.566 ; gain = 225.105 ; free physical = 8078 ; free virtual = 43238 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8078 ; free virtual = 43238 INFO: [Project 1-571] Translating synthesized netlist Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8043 ; free virtual = 43202 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8036 ; free virtual = 43196 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8036 ; free virtual = 43196 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 4 Rip-up And Reroute | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8036 ; free virtual = 43196 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8050 ; free virtual = 43210 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8059 ; free virtual = 43219 Phase 6 Post Hold Fix | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8059 ; free virtual = 43219 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 543.246 ; free physical = 8035 ; free virtual = 43195 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.324 ; gain = 623.949 ; free physical = 8033 ; free virtual = 43192 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8024 ; free virtual = 43184 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 8003 ; free virtual = 43163 Phase 9 Depositing Routes INFO: [Project 1-570] Preparing netlist for logic optimization Phase 9 Depositing Routes | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 7920 ; free virtual = 43080 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2177.992 ; gain = 93.586 ; free physical = 7959 ; free virtual = 43119 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:46 . Memory (MB): peak = 2216.781 ; gain = 164.391 ; free physical = 7955 ; free virtual = 43115 Writing placer database... Writing bitstream ./design.bit... INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 8252 ; free virtual = 43427 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 8118 ; free virtual = 43300 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 165c53615 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 8119 ; free virtual = 43301 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2216.781 ; gain = 0.000 ; free physical = 8092 ; free virtual = 43284 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 8092 ; free virtual = 43285 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2216.781 ; gain = 0.000 ; free physical = 8066 ; free virtual = 43233 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:27:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 8056 ; free virtual = 43223 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:27:49 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1483.746 ; gain = 0.000 ; free physical = 8627 ; free virtual = 43794 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1483.746 ; gain = 0.000 ; free physical = 8979 ; free virtual = 44146 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Running DRC as a precondition to command write_bitstream 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.590 ; gain = 333.695 ; free physical = 9037 ; free virtual = 44204 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1483.621 ; gain = 0.000 ; free physical = 8933 ; free virtual = 44100 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1483.621 ; gain = 0.000 ; free physical = 8929 ; free virtual = 44096 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1 Build RT Design | Checksum: 1307d6b8e Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2057.922 ; gain = 93.668 ; free physical = 8852 ; free virtual = 44020 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1307d6b8e Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2063.910 ; gain = 99.656 ; free physical = 8799 ; free virtual = 43967 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1307d6b8e Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2063.910 ; gain = 99.656 ; free physical = 8796 ; free virtual = 43964 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6d37d05e Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.965 ; gain = 105.711 ; free physical = 8827 ; free virtual = 43995 Phase 3 Initial Routing 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 8840 ; free virtual = 44008 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.965 ; gain = 105.711 ; free physical = 8756 ; free virtual = 43923 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.965 ; gain = 105.711 ; free physical = 8731 ; free virtual = 43898 Phase 4 Rip-up And Reroute | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.965 ; gain = 105.711 ; free physical = 8731 ; free virtual = 43898 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.965 ; gain = 105.711 ; free physical = 8730 ; free virtual = 43897 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.965 ; gain = 105.711 ; free physical = 8729 ; free virtual = 43896 Phase 6 Post Hold Fix | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.965 ; gain = 105.711 ; free physical = 8727 ; free virtual = 43894 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.965 ; gain = 105.711 ; free physical = 8625 ; free virtual = 43792 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2072.965 ; gain = 108.711 ; free physical = 8623 ; free virtual = 43791 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2072.965 ; gain = 108.711 ; free physical = 8621 ; free virtual = 43788 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2072.965 ; gain = 108.711 ; free physical = 8650 ; free virtual = 43817 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2111.754 ; gain = 179.516 ; free physical = 8649 ; free virtual = 43817 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2111.754 ; gain = 0.000 ; free physical = 8437 ; free virtual = 43606 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.199 ; gain = 0.000 ; free physical = 8269 ; free virtual = 43437 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8141 ; free virtual = 43308 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8137 ; free virtual = 43305 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8137 ; free virtual = 43304 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8136 ; free virtual = 43303 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8135 ; free virtual = 43302 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8134 ; free virtual = 43302 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 534.562 ; free physical = 8134 ; free virtual = 43302 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 8128 ; free virtual = 43296 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1544.859 ; gain = 0.000 ; free physical = 8085 ; free virtual = 43253 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.58 . Memory (MB): peak = 1544.859 ; gain = 0.000 ; free physical = 8116 ; free virtual = 43283 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 8053 ; free virtual = 43220 Phase 1.3 Build Placer Netlist Model INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 7653 ; free virtual = 42821 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 7603 ; free virtual = 42771 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 7585 ; free virtual = 42753 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 7541 ; free virtual = 42709 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 502.531 ; free physical = 7544 ; free virtual = 42711 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 7541 ; free virtual = 42708 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 7078 ; free virtual = 42246 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e0a71f46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 6942 ; free virtual = 42110 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 6916 ; free virtual = 42084 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 6945 ; free virtual = 42113 Phase 1 Placer Initialization | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 6943 ; free virtual = 42111 Phase 2 Global Placement Phase 1 Build RT Design | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2134.090 ; gain = 49.668 ; free physical = 6794 ; free virtual = 41962 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2143.078 ; gain = 58.656 ; free physical = 6643 ; free virtual = 41811 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2143.078 ; gain = 58.656 ; free physical = 6630 ; free virtual = 41798 Loading site data... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.234 ; gain = 0.000 ; free physical = 6326 ; free virtual = 41494 Phase 2 Router Initialization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6324 ; free virtual = 41492 Phase 3 Initial Routing Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading route data... Processing options... Creating bitmap... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 510.531 ; free physical = 6143 ; free virtual = 41311 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 510.531 ; free physical = 6103 ; free virtual = 41270 Phase 1.4 Constrain Clocks/Macros Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6095 ; free virtual = 41262 Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 510.531 ; free physical = 6112 ; free virtual = 41280 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 510.531 ; free physical = 6102 ; free virtual = 41270 Phase 2 Final Placement Cleanup Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 510.531 ; free physical = 6089 ; free virtual = 41257 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 510.531 ; free physical = 6091 ; free virtual = 41259 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.277 ; gain = 577.562 ; free physical = 6091 ; free virtual = 41258 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.1 Global Iteration 0 | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6087 ; free virtual = 41255 Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Rip-up And Reroute | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6077 ; free virtual = 41245 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6072 ; free virtual = 41239 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6066 ; free virtual = 41234 Phase 6 Post Hold Fix | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6060 ; free virtual = 41228 Phase 7 Route finalize INFO: [Timing 38-35] Done setting XDC timing constraints. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6029 ; free virtual = 41197 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6025 ; free virtual = 41193 Phase 9 Depositing Routes INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.109 ; gain = 0.000 ; free physical = 6024 ; free virtual = 41192 Loading site data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 509.531 ; free physical = 5985 ; free virtual = 41153 Phase 1.3 Build Placer Netlist Model Phase 9 Depositing Routes | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6018 ; free virtual = 41186 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2179.508 ; gain = 95.086 ; free physical = 6060 ; free virtual = 41228 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:53 . Memory (MB): peak = 2218.297 ; gain = 165.891 ; free physical = 6059 ; free virtual = 41227 Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 509.531 ; free physical = 6058 ; free virtual = 41226 Phase 1.4 Constrain Clocks/Macros Phase 2 Global Placement | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6058 ; free virtual = 41226 Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 509.531 ; free physical = 6057 ; free virtual = 41225 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 509.531 ; free physical = 6055 ; free virtual = 41223 Phase 2 Final Placement Cleanup Phase 3.1 Commit Multi Column Macros | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6054 ; free virtual = 41222 Phase 3.2 Commit Most Macros & LUTRAMs Processing options... Creating bitmap... Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 509.531 ; free physical = 6051 ; free virtual = 41219 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 509.531 ; free physical = 6053 ; free virtual = 41220 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.152 ; gain = 576.562 ; free physical = 6053 ; free virtual = 41220 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2433660c9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6055 ; free virtual = 41223 Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d113e94 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6052 ; free virtual = 41220 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e6c59ef9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6050 ; free virtual = 41219 Phase 3.5 Small Shape Detail Placement Writing placer database... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Creating bitstream... Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.5 Small Shape Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6033 ; free virtual = 41205 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6031 ; free virtual = 41202 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6030 ; free virtual = 41202 Phase 3 Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6028 ; free virtual = 41199 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6021 ; free virtual = 41193 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6016 ; free virtual = 41188 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6016 ; free virtual = 41188 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6015 ; free virtual = 41187 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6014 ; free virtual = 41185 Ending Placer Task | Checksum: 1d0f627a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 6027 ; free virtual = 41198 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 6027 ; free virtual = 41198 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec567e97 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4192 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2218.297 ; gain = 0.000 ; free physical = 5898 ; free virtual = 41098 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2218.297 ; gain = 0.000 ; free physical = 5790 ; free virtual = 40965 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:28:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2455.859 ; gain = 344.105 ; free physical = 5782 ; free virtual = 40957 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:28:22 2019... Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 5802 ; free virtual = 40977 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_013 Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 507.531 ; free physical = 6458 ; free virtual = 41634 Phase 1.3 Build Placer Netlist Model Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2061.922 ; gain = 43.668 ; free physical = 6414 ; free virtual = 41590 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.910 ; gain = 49.656 ; free physical = 6373 ; free virtual = 41549 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.910 ; gain = 49.656 ; free physical = 6373 ; free virtual = 41549 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 6357 ; free virtual = 41533 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 6338 ; free virtual = 41514 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 6337 ; free virtual = 41513 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 6337 ; free virtual = 41513 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 6337 ; free virtual = 41513 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 6337 ; free virtual = 41513 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 6336 ; free virtual = 41512 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 6331 ; free virtual = 41507 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 6330 ; free virtual = 41506 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 6324 ; free virtual = 41500 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 6359 ; free virtual = 41535 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2120.754 ; gain = 134.516 ; free physical = 6358 ; free virtual = 41534 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2120.754 ; gain = 0.000 ; free physical = 6352 ; free virtual = 41531 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 1151.434 ; gain = 55.992 ; free physical = 6343 ; free virtual = 41521 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.391 ; gain = 507.531 ; free physical = 6603 ; free virtual = 41784 Phase 1.4 Constrain Clocks/Macros Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.391 ; gain = 507.531 ; free physical = 6600 ; free virtual = 41780 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.391 ; gain = 507.531 ; free physical = 6599 ; free virtual = 41780 Phase 2 Final Placement Cleanup WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.391 ; gain = 507.531 ; free physical = 6599 ; free virtual = 41780 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2] Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.391 ; gain = 507.531 ; free physical = 6590 ; free virtual = 41771 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 6589 ; free virtual = 41770 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1211.941 ; gain = 116.500 ; free physical = 6540 ; free virtual = 41722 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1211.941 ; gain = 116.500 ; free physical = 6639 ; free virtual = 41820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.969 ; gain = 124.527 ; free physical = 6635 ; free virtual = 41816 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1219.969 ; gain = 124.527 ; free physical = 6499 ; free virtual = 41680 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:28:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:46 . Memory (MB): peak = 2606.902 ; gain = 390.121 ; free physical = 6394 ; free virtual = 41575 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:28:34 2019... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Loading data files... Loading data files... touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_014 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2130.086 ; gain = 38.762 ; free physical = 7358 ; free virtual = 42539 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2136.074 ; gain = 44.750 ; free physical = 7321 ; free virtual = 42502 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2136.074 ; gain = 44.750 ; free physical = 7321 ; free virtual = 42502 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7285 ; free virtual = 42467 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7216 ; free virtual = 42398 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7213 ; free virtual = 42395 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7212 ; free virtual = 42395 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7212 ; free virtual = 42395 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7212 ; free virtual = 42395 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7212 ; free virtual = 42395 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7207 ; free virtual = 42389 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7205 ; free virtual = 42387 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7203 ; free virtual = 42386 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 7232 ; free virtual = 42414 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:56 . Memory (MB): peak = 2193.918 ; gain = 102.594 ; free physical = 7232 ; free virtual = 42414 Writing placer database... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.918 ; gain = 0.000 ; free physical = 6991 ; free virtual = 42195 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.680 ; gain = 216.238 ; free physical = 6980 ; free virtual = 42185 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.680 ; gain = 216.238 ; free physical = 6969 ; free virtual = 42175 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6961 ; free virtual = 42144 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6881 ; free virtual = 42065 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6878 ; free virtual = 42061 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6875 ; free virtual = 42058 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6875 ; free virtual = 42058 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6873 ; free virtual = 42057 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6872 ; free virtual = 42056 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6872 ; free virtual = 42055 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 6868 ; free virtual = 42052 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 6870 ; free virtual = 42054 INFO: [Project 1-571] Translating synthesized netlist Loading site data... Loading site data... Loading route data... Loading route data... Processing options... Creating bitmap... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2055.926 ; gain = 91.668 ; free physical = 6579 ; free virtual = 41762 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 133887d51 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2062.914 ; gain = 98.656 ; free physical = 6544 ; free virtual = 41728 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 133887d51 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2062.914 ; gain = 98.656 ; free physical = 6544 ; free virtual = 41728 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6484 ; free virtual = 41668 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6473 ; free virtual = 41656 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6469 ; free virtual = 41652 Phase 4 Rip-up And Reroute | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6469 ; free virtual = 41652 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6469 ; free virtual = 41652 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6470 ; free virtual = 41653 Phase 6 Post Hold Fix | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6469 ; free virtual = 41653 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6571 ; free virtual = 41754 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 6570 ; free virtual = 41754 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f6c26eb9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 6569 ; free virtual = 41752 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 6603 ; free virtual = 41786 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2110.758 ; gain = 178.516 ; free physical = 6602 ; free virtual = 41786 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2110.758 ; gain = 0.000 ; free physical = 6554 ; free virtual = 41739 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4548 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading data files... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1416.703 ; gain = 333.820 ; free physical = 6382 ; free virtual = 41566 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1481.734 ; gain = 0.000 ; free physical = 6280 ; free virtual = 41463 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1481.734 ; gain = 0.000 ; free physical = 6279 ; free virtual = 41463 Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Writing bitstream ./design.bit... Creating bitstream... Phase 1 Build RT Design | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2134.078 ; gain = 49.668 ; free physical = 6148 ; free virtual = 41336 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1b23f6d9e Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 6309 ; free virtual = 41496 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1b23f6d9e Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 6306 ; free virtual = 41493 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1cdf75140 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6229 ; free virtual = 41417 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6200 ; free virtual = 41388 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6197 ; free virtual = 41385 Phase 4 Rip-up And Reroute | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6196 ; free virtual = 41384 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6196 ; free virtual = 41384 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6196 ; free virtual = 41384 Phase 6 Post Hold Fix | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6196 ; free virtual = 41384 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6182 ; free virtual = 41370 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6181 ; free virtual = 41368 Phase 9 Depositing Routes Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 6126 ; free virtual = 41314 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 1cdf75140 Time (s): cpu = 00:00:46 ; elapsed = 00:00:55 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6125 ; free virtual = 41313 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:46 ; elapsed = 00:00:55 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 6192 ; free virtual = 41380 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:58 . Memory (MB): peak = 2217.785 ; gain = 165.391 ; free physical = 6192 ; free virtual = 41380 Writing bitstream ./design.bit... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4644 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:29:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2459.859 ; gain = 339.105 ; free physical = 6404 ; free virtual = 41600 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:29:02 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading route data... Processing options... Creating bitmap... touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 21992 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_016 Phase 1 Build RT Design | Checksum: 10fbb77b1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 7254 ; free virtual = 42463 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10fbb77b1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 7209 ; free virtual = 42419 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10fbb77b1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 7207 ; free virtual = 42418 Phase 1 Build RT Design | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.961 ; gain = 41.668 ; free physical = 7186 ; free virtual = 42399 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2074.949 ; gain = 48.656 ; free physical = 7143 ; free virtual = 42356 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2074.949 ; gain = 48.656 ; free physical = 7144 ; free virtual = 42357 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174384e93 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7175 ; free virtual = 42392 Phase 3 Initial Routing Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.785 ; gain = 0.000 ; free physical = 7132 ; free virtual = 42353 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.254 ; gain = 60.961 ; free physical = 7154 ; free virtual = 42375 Phase 3 Initial Routing Phase 1 Build RT Design | Checksum: 15af38611 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2066.836 ; gain = 41.668 ; free physical = 7145 ; free virtual = 42366 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15af38611 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2073.824 ; gain = 48.656 ; free physical = 7112 ; free virtual = 42333 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15af38611 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2073.824 ; gain = 48.656 ; free physical = 7112 ; free virtual = 42333 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7105 ; free virtual = 42327 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7103 ; free virtual = 42324 Phase 4 Rip-up And Reroute | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7103 ; free virtual = 42324 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7103 ; free virtual = 42324 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7103 ; free virtual = 42324 Phase 6 Post Hold Fix | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7103 ; free virtual = 42324 Phase 7 Route finalize Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7101 ; free virtual = 42323 Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7097 ; free virtual = 42319 Phase 4 Rip-up And Reroute | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7096 ; free virtual = 42318 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7096 ; free virtual = 42317 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 6.1 Hold Fix Iter | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7095 ; free virtual = 42317 Phase 6 Post Hold Fix | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.254 ; gain = 61.961 ; free physical = 7095 ; free virtual = 42317 Phase 7 Route finalize | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7093 ; free virtual = 42315 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7091 ; free virtual = 42313 Phase 9 Depositing Routes Phase 7 Route finalize Phase 9 Depositing Routes | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7089 ; free virtual = 42311 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7126 ; free virtual = 42348 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2140.016 ; gain = 47.473 ; free physical = 7125 ; free virtual = 42347 Creating bitstream... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2089.254 ; gain = 62.961 ; free physical = 7113 ; free virtual = 42335 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2091.254 ; gain = 64.961 ; free physical = 7109 ; free virtual = 42331 Phase 9 Depositing Routes Writing placer database... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2086.129 ; gain = 60.961 ; free physical = 7092 ; free virtual = 42315 Phase 3 Initial Routing Writing XDEF routing. Phase 9 Depositing Routes | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2092.254 ; gain = 65.961 ; free physical = 7090 ; free virtual = 42314 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:29:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2092.254 ; gain = 65.961 ; free physical = 7131 ; free virtual = 42356 Routing Is Done. Writing XDEF routing logical nets. Writing XDEF routing special nets. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2131.043 ; gain = 136.766 ; free physical = 7128 ; free virtual = 42353 Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 7129 ; free virtual = 42355 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:16] 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:46 . Memory (MB): peak = 2606.457 ; gain = 388.160 ; free physical = 7130 ; free virtual = 42357 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:29:07 2019... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2217.785 ; gain = 0.000 ; free physical = 7161 ; free virtual = 42357 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2131.043 ; gain = 0.000 ; free physical = 7206 ; free virtual = 42404 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.129 ; gain = 63.961 ; free physical = 7211 ; free virtual = 42409 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.129 ; gain = 63.961 ; free physical = 7215 ; free virtual = 42413 Phase 4 Rip-up And Reroute | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.129 ; gain = 63.961 ; free physical = 7222 ; free virtual = 42420 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.129 ; gain = 63.961 ; free physical = 7277 ; free virtual = 42475 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.129 ; gain = 63.961 ; free physical = 7406 ; free virtual = 42604 Phase 6 Post Hold Fix | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.129 ; gain = 63.961 ; free physical = 7518 ; free virtual = 42716 Phase 7 Route finalize Loading site data... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Bitstream size: 4243411 bytes WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:7] Config size: 1060815 words Number of configuration frames: 9996 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] Phase 7 Route finalize | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.129 ; gain = 63.961 ; free physical = 8126 ; free virtual = 43324 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2091.129 ; gain = 65.961 ; free physical = 8130 ; free virtual = 43328 Phase 9 Depositing Routes DONE Loading route data... Processing options... Creating bitmap... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2091.129 ; gain = 65.961 ; free physical = 8198 ; free virtual = 43396 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2091.129 ; gain = 65.961 ; free physical = 8233 ; free virtual = 43432 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:55 . Memory (MB): peak = 2129.918 ; gain = 136.766 ; free physical = 8224 ; free virtual = 43423 Writing placer database... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8164 ; free virtual = 43361 --------------------------------------------------------------------------------- touch build/specimen_011/OK Running DRC as a precondition to command write_bitstream GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2129.918 ; gain = 0.000 ; free physical = 8206 ; free virtual = 43407 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8122 ; free virtual = 43323 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 8119 ; free virtual = 43321 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:29:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2532.023 ; gain = 338.105 ; free physical = 8328 ; free virtual = 43530 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:29:13 2019... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 8291 ; free virtual = 43493 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9274 ; free virtual = 44479 --------------------------------------------------------------------------------- touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_017 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.223 ; gain = 0.000 ; free physical = 9010 ; free virtual = 44216 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 512.531 ; free physical = 8967 ; free virtual = 44173 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 512.531 ; free physical = 8954 ; free virtual = 44161 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 512.531 ; free physical = 8949 ; free virtual = 44155 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 512.531 ; free physical = 8942 ; free virtual = 44148 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 512.531 ; free physical = 8935 ; free virtual = 44141 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 512.531 ; free physical = 8929 ; free virtual = 44135 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.266 ; gain = 577.562 ; free physical = 8927 ; free virtual = 44133 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:29:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2452.863 ; gain = 342.105 ; free physical = 8810 ; free virtual = 44016 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:29:17 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9590 ; free virtual = 44796 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:16] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9512 ; free virtual = 44719 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9513 ; free virtual = 44724 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9443 ; free virtual = 44655 --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9452 ; free virtual = 44664 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 9452 ; free virtual = 44664 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9454 ; free virtual = 44666 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9445 ; free virtual = 44657 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9441 ; free virtual = 44654 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9440 ; free virtual = 44653 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9440 ; free virtual = 44652 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9439 ; free virtual = 44651 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9437 ; free virtual = 44650 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9436 ; free virtual = 44648 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 9436 ; free virtual = 44648 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 8963 ; free virtual = 44175 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: e9c56990 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2134.074 ; gain = 49.668 ; free physical = 8924 ; free virtual = 44137 Loading site data... Loading site data... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Loading route data... Processing options... Phase 2.1 Fix Topology Constraints | Checksum: e9c56990 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8794 ; free virtual = 44006 Phase 2.2 Pre Route Cleanup Creating bitmap... Phase 2.2 Pre Route Cleanup | Checksum: e9c56990 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8790 ; free virtual = 44003 Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8583 ; free virtual = 43796 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8501 ; free virtual = 43713 Loading site data... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8495 ; free virtual = 43708 Phase 4 Rip-up And Reroute | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8494 ; free virtual = 43706 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8492 ; free virtual = 43704 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8490 ; free virtual = 43703 Phase 6 Post Hold Fix | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8488 ; free virtual = 43701 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8458 ; free virtual = 43671 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8450 ; free virtual = 43663 Phase 9 Depositing Routes Loading route data... Processing options... Creating bitmap... Phase 9 Depositing Routes | Checksum: 16f7d8d1d Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8417 ; free virtual = 43629 INFO: [Route 35-16] Router Completed Successfully ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl Time (s): cpu = 00:00:46 ; elapsed = 00:00:53 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 8459 ; free virtual = 43671 Routing Is Done.# source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2217.781 ; gain = 165.391 ; free physical = 8453 ; free virtual = 43665 Writing placer database... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5098 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8140 ; free virtual = 43373 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8117 ; free virtual = 43351 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading site data... Creating bitstream... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8077 ; free virtual = 43313 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Writing XDEF routing. Processing options... Creating bitmap... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 8041 ; free virtual = 43282 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7926 ; free virtual = 43168 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7924 ; free virtual = 43165 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5148 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7929 ; free virtual = 43171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7928 ; free virtual = 43170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7928 ; free virtual = 43170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7928 ; free virtual = 43170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7928 ; free virtual = 43170 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7981 ; free virtual = 43223 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 7982 ; free virtual = 43225 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 7988 ; free virtual = 43203 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 7985 ; free virtual = 43201 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks Creating bitstream... INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing bitstream ./design.bit... WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-570] Preparing netlist for logic optimization Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Creating bitstream... Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1545.953 ; gain = 0.000 ; free physical = 8000 ; free virtual = 43220 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.97 . Memory (MB): peak = 1545.953 ; gain = 0.000 ; free physical = 8098 ; free virtual = 43318 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5241 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:29:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2474.121 ; gain = 334.105 ; free physical = 8415 ; free virtual = 43643 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:29:44 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 8714 ; free virtual = 43942 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 22337 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_015 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] Creating bitstream... WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9484 ; free virtual = 44714 --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9475 ; free virtual = 44705 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9473 ; free virtual = 44704 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9454 ; free virtual = 44684 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:29:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2469.023 ; gain = 339.105 ; free physical = 9401 ; free virtual = 44631 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:29:46 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:29:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2469.148 ; gain = 338.105 ; free physical = 9459 ; free virtual = 44688 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:29:47 2019... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 10397 ; free virtual = 45626 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5374 touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_018 touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_019 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Writing bitstream ./design.bit... 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:47 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 11268 ; free virtual = 46502 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 11521 ; free virtual = 46759 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 11636 ; free virtual = 46873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.949 ; gain = 0.000 ; free physical = 11635 ; free virtual = 46873 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 11633 ; free virtual = 46871 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1549.949 ; gain = 0.000 ; free physical = 11603 ; free virtual = 46841 Loading data files... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 11603 ; free virtual = 46840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11567 ; free virtual = 46804 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11373 ; free virtual = 46611 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11369 ; free virtual = 46610 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11368 ; free virtual = 46610 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11370 ; free virtual = 46608 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11339 ; free virtual = 46577 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11329 ; free virtual = 46567 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:29:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:46 . Memory (MB): peak = 2607.945 ; gain = 390.160 ; free physical = 11335 ; free virtual = 46573 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11335 ; free virtual = 46572 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:29:53 2019... --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12330 ; free virtual = 47567 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12323 ; free virtual = 47560 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12312 ; free virtual = 47548 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12306 ; free virtual = 47543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12293 ; free virtual = 47529 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12294 ; free virtual = 47531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12312 ; free virtual = 47548 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12314 ; free virtual = 47550 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 12314 ; free virtual = 47551 INFO: [Project 1-571] Translating synthesized netlist touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 11996 ; free virtual = 47239 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 11905 ; free virtual = 47147 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 11756 ; free virtual = 46998 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11755 ; free virtual = 46998 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 11542 ; free virtual = 46784 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11459 ; free virtual = 46702 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11450 ; free virtual = 46692 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11439 ; free virtual = 46681 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11436 ; free virtual = 46679 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11436 ; free virtual = 46678 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11435 ; free virtual = 46677 WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:211] +-+--------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11434 ; free virtual = 46677 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 11430 ; free virtual = 46673 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 11429 ; free virtual = 46672 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 11335 ; free virtual = 46578 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 11346 ; free virtual = 46589 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 11344 ; free virtual = 46587 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 11217 ; free virtual = 46460 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 11251 ; free virtual = 46494 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11239 ; free virtual = 46482 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 11265 ; free virtual = 46508 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11263 ; free virtual = 46506 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11263 ; free virtual = 46506 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11263 ; free virtual = 46506 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11262 ; free virtual = 46505 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11260 ; free virtual = 46502 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11260 ; free virtual = 46502 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11258 ; free virtual = 46500 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11257 ; free virtual = 46500 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 11257 ; free virtual = 46500 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 10904 ; free virtual = 46147 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 10866 ; free virtual = 46108 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5698 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 10827 ; free virtual = 46070 Phase 2 Global Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1 Build RT Design | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2066.949 ; gain = 40.668 ; free physical = 10780 ; free virtual = 46023 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2073.938 ; gain = 47.656 ; free physical = 10752 ; free virtual = 45995 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2073.938 ; gain = 47.656 ; free physical = 10751 ; free virtual = 45994 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 10747 ; free virtual = 45990 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12bd49b1d Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2087.242 ; gain = 60.961 ; free physical = 10596 ; free virtual = 45839 Phase 3 Initial Routing ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 10593 ; free virtual = 45836 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.242 ; gain = 62.961 ; free physical = 10466 ; free virtual = 45709 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.242 ; gain = 62.961 ; free physical = 10458 ; free virtual = 45701 Phase 4 Rip-up And Reroute | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.242 ; gain = 62.961 ; free physical = 10459 ; free virtual = 45702 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.242 ; gain = 62.961 ; free physical = 10459 ; free virtual = 45702 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.242 ; gain = 62.961 ; free physical = 10459 ; free virtual = 45702 Phase 6 Post Hold Fix | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.242 ; gain = 62.961 ; free physical = 10459 ; free virtual = 45702 Phase 7 Route finalize INFO: [Timing 38-35] Done setting XDC timing constraints. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2089.242 ; gain = 62.961 ; free physical = 10456 ; free virtual = 45699 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2092.242 ; gain = 65.961 ; free physical = 10456 ; free virtual = 45699 Phase 9 Depositing Routes Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2092.242 ; gain = 65.961 ; free physical = 10400 ; free virtual = 45643 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:52 . Memory (MB): peak = 2092.242 ; gain = 65.961 ; free physical = 10433 ; free virtual = 45676 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2131.031 ; gain = 136.766 ; free physical = 10432 ; free virtual = 45675 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 10431 ; free virtual = 45674 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 10437 ; free virtual = 45680 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 10466 ; free virtual = 45709 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Placer Task Writing XDEF routing. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 1.1 Placer Initialization Netlist Sorting INFO: Launching helper process for spawning children vivado processes Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1483.742 ; gain = 0.000 ; free physical = 10408 ; free virtual = 45653 Write XDEF Complete: Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2131.031 ; gain = 0.000 ; free physical = 10392 ; free virtual = 45638 INFO: Helper process launched with PID 6477 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1483.742 ; gain = 0.000 ; free physical = 10381 ; free virtual = 45627 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 6567 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10319 ; free virtual = 45562 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 10317 ; free virtual = 45561 Phase 1.3 Build Placer Netlist Model Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10316 ; free virtual = 45559 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10279 ; free virtual = 45523 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10227 ; free virtual = 45470 Phase 3.4 Pipeline Register Optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10202 ; free virtual = 45446 Phase 3.5 Small Shape Detail Placement INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 10487 ; free virtual = 45755 Phase 1.4 Constrain Clocks/Macros Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10474 ; free virtual = 45743 Phase 3.6 Re-assign LUT pins --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 10481 ; free virtual = 45730 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 10445 ; free virtual = 45695 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10441 ; free virtual = 45691 Phase 3.7 Pipeline Register Optimization Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 10482 ; free virtual = 45732 Phase 2 Global Placement Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10492 ; free virtual = 45741 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10494 ; free virtual = 45763 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10434 ; free virtual = 45703 Phase 4.2 Post Placement Cleanup Loading data files... Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10429 ; free virtual = 45697 Phase 4.3 Placer Reporting --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 10386 ; free virtual = 45655 --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10383 ; free virtual = 45653 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 10397 ; free virtual = 45646 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 10396 ; free virtual = 45645 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10390 ; free virtual = 45640 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10335 ; free virtual = 45584 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 10321 ; free virtual = 45571 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 10320 ; free virtual = 45569 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:30:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:43 . Memory (MB): peak = 2605.902 ; gain = 388.121 ; free physical = 10087 ; free virtual = 45336 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:30:19 2019... Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10139 ; free virtual = 45387 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10516 ; free virtual = 45764 Phase 3.2 Commit Most Macros & LUTRAMs WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Bitstream size: 4243411 bytes Starting Routing Task Config size: 1060815 words Number of configuration frames: 9996 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs DONE --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11139 ; free virtual = 46387 --------------------------------------------------------------------------------- Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 11091 ; free virtual = 46340 INFO: Launching helper process for spawning children vivado processes Phase 3.3 Area Swap Optimization INFO: Helper process launched with PID 7417 touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_016 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10959 ; free virtual = 46209 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10851 ; free virtual = 46100 Phase 3.5 Small Shape Detail Placement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 10777 ; free virtual = 46027 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10723 ; free virtual = 45977 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10802 ; free virtual = 46057 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10795 ; free virtual = 46050 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10794 ; free virtual = 46049 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10779 ; free virtual = 46034 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10775 ; free virtual = 46030 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10772 ; free virtual = 46027 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10772 ; free virtual = 46027 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10771 ; free virtual = 46026 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10771 ; free virtual = 46026 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10772 ; free virtual = 46027 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 10772 ; free virtual = 46027 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 10755 ; free virtual = 46010 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10734 ; free virtual = 45989 Phase 3.6 Re-assign LUT pins WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:16] Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10701 ; free virtual = 45956 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10680 ; free virtual = 45935 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10658 ; free virtual = 45913 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10634 ; free virtual = 45889 Phase 4.2 Post Placement Cleanup INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:2] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10657 ; free virtual = 45912 Starting Routing Task Phase 4.3 Placer Reporting INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10686 ; free virtual = 45942 --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10670 ; free virtual = 45927 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10673 ; free virtual = 45931 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10659 ; free virtual = 45917 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10647 ; free virtual = 45908 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10631 ; free virtual = 45893 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 10629 ; free virtual = 45885 --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10626 ; free virtual = 45882 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 549.250 ; free physical = 10621 ; free virtual = 45883 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 631.953 ; free physical = 10619 ; free virtual = 45881 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 10584 ; free virtual = 45840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 10584 ; free virtual = 45839 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 10383 ; free virtual = 45639 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 10325 ; free virtual = 45581 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading site data... Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 10149 ; free virtual = 45405 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9945 ; free virtual = 45201 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 9501 ; free virtual = 44756 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.203 ; gain = 0.000 ; free physical = 9498 ; free virtual = 44754 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 9469 ; free virtual = 44725 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9468 ; free virtual = 44723 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 9467 ; free virtual = 44723 Phase 1.4 Constrain Clocks/Macros Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9465 ; free virtual = 44720 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 9460 ; free virtual = 44716 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 9457 ; free virtual = 44716 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 9448 ; free virtual = 44709 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 9454 ; free virtual = 44710 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 9454 ; free virtual = 44710 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9449 ; free virtual = 44705 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9438 ; free virtual = 44694 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9416 ; free virtual = 44672 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9407 ; free virtual = 44663 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9405 ; free virtual = 44661 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9398 ; free virtual = 44654 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 9398 ; free virtual = 44654 INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9361 ; free virtual = 44617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9339 ; free virtual = 44595 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 9341 ; free virtual = 44597 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.246 ; gain = 468.531 ; free physical = 9329 ; free virtual = 44585 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9329 ; free virtual = 44585 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.246 ; gain = 468.531 ; free physical = 9327 ; free virtual = 44583 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.246 ; gain = 468.531 ; free physical = 9327 ; free virtual = 44583 Phase 1 Placer Initialization | Checksum: 1d21143fb --------------------------------------------------------------------------------- Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.246 ; gain = 468.531 ; free physical = 9327 ; free virtual = 44583 Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.246 ; gain = 468.531 ; free physical = 9326 ; free virtual = 44582 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.246 ; gain = 468.531 ; free physical = 9327 ; free virtual = 44583 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1931.246 ; gain = 533.562 ; free physical = 9327 ; free virtual = 44583 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9253 ; free virtual = 44509 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9252 ; free virtual = 44508 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9252 ; free virtual = 44508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9252 ; free virtual = 44507 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9251 ; free virtual = 44507 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9251 ; free virtual = 44507 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9251 ; free virtual = 44506 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9248 ; free virtual = 44504 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 9250 ; free virtual = 44506 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9226 ; free virtual = 44482 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Starting Routing Task --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9220 ; free virtual = 44476 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9215 ; free virtual = 44471 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9113 ; free virtual = 44369 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9113 ; free virtual = 44369 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9112 ; free virtual = 44368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9112 ; free virtual = 44368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9112 ; free virtual = 44368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9112 ; free virtual = 44368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9111 ; free virtual = 44367 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9111 ; free virtual = 44367 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 9111 ; free virtual = 44367 INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.566 ; gain = 248.945 ; free physical = 9077 ; free virtual = 44333 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.566 ; gain = 248.945 ; free physical = 9075 ; free virtual = 44331 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 9014 ; free virtual = 44270 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 8838 ; free virtual = 44094 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8891 ; free virtual = 44147 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8886 ; free virtual = 44142 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8854 ; free virtual = 44110 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8847 ; free virtual = 44103 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8835 ; free virtual = 44091 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8805 ; free virtual = 44061 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8827 ; free virtual = 44085 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 8820 ; free virtual = 44076 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.598 ; gain = 269.969 ; free physical = 8821 ; free virtual = 44077 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing bitstream ./design.bit... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 8693 ; free virtual = 43951 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 8693 ; free virtual = 43950 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 8762 ; free virtual = 44022 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 8934 ; free virtual = 44194 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 8931 ; free virtual = 44191 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:30:44 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.137 ; gain = 339.105 ; free physical = 8758 ; free virtual = 44018 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:30:44 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_016 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 9494 ; free virtual = 44758 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7879 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:45 . Memory (MB): peak = 1467.262 ; gain = 384.367 ; free physical = 9484 ; free virtual = 44768 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 9506 ; free virtual = 44771 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 9506 ; free virtual = 44770 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1545.965 ; gain = 0.000 ; free physical = 9403 ; free virtual = 44667 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1545.965 ; gain = 0.000 ; free physical = 9393 ; free virtual = 44658 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 9245 ; free virtual = 44510 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 9219 ; free virtual = 44484 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 8815 ; free virtual = 44080 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 8867 ; free virtual = 44132 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 8819 ; free virtual = 44084 --------------------------------------------------------------------------------- Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1554.859 ; gain = 0.000 ; free physical = 8787 ; free virtual = 44052 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1554.859 ; gain = 0.000 ; free physical = 8771 ; free virtual = 44035 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8771 ; free virtual = 44035 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8766 ; free virtual = 44031 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8766 ; free virtual = 44030 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8765 ; free virtual = 44029 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8764 ; free virtual = 44028 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8762 ; free virtual = 44027 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 8762 ; free virtual = 44026 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 8725 ; free virtual = 43989 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8481 ; free virtual = 43746 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 8456 ; free virtual = 43720 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8425 ; free virtual = 43690 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8421 ; free virtual = 43685 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8421 ; free virtual = 43685 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8421 ; free virtual = 43685 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8420 ; free virtual = 43685 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8420 ; free virtual = 43685 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 8420 ; free virtual = 43685 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8406 ; free virtual = 43670 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8397 ; free virtual = 43661 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8387 ; free virtual = 43651 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8381 ; free virtual = 43645 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8382 ; free virtual = 43646 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8380 ; free virtual = 43644 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8378 ; free virtual = 43643 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8379 ; free virtual = 43644 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 8380 ; free virtual = 43644 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2131.430 ; gain = 32.227 ; free physical = 8345 ; free virtual = 43610 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2137.418 ; gain = 38.215 ; free physical = 8310 ; free virtual = 43574 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2137.418 ; gain = 38.215 ; free physical = 8310 ; free virtual = 43574 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8267 ; free virtual = 43532 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8262 ; free virtual = 43527 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8262 ; free virtual = 43526 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8262 ; free virtual = 43526 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8262 ; free virtual = 43526 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8260 ; free virtual = 43524 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8260 ; free virtual = 43524 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8253 ; free virtual = 43517 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8251 ; free virtual = 43515 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8249 ; free virtual = 43514 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2157.473 ; gain = 58.270 ; free physical = 8284 ; free virtual = 43548 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:50 . Memory (MB): peak = 2196.262 ; gain = 97.059 ; free physical = 8284 ; free virtual = 43548 Writing placer database... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 1 Build RT Design | Checksum: 972cf7e0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 8236 ; free virtual = 43508 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 972cf7e0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 8203 ; free virtual = 43476 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 972cf7e0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 8203 ; free virtual = 43476 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 155c195dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8140 ; free virtual = 43416 Phase 3 Initial Routing INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8053 ; free virtual = 43331 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8024 ; free virtual = 43303 Phase 4 Rip-up And Reroute | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8022 ; free virtual = 43301 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8020 ; free virtual = 43299 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8017 ; free virtual = 43296 Phase 6 Post Hold Fix | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8023 ; free virtual = 43302 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 8035 ; free virtual = 43315 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 8032 ; free virtual = 43312 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 8031 ; free virtual = 43311 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 8063 ; free virtual = 43343 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2111.766 ; gain = 179.516 ; free physical = 8060 ; free virtual = 43340 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8061 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2111.766 ; gain = 0.000 ; free physical = 8047 ; free virtual = 43329 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2196.262 ; gain = 0.000 ; free physical = 7897 ; free virtual = 43186 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1905.453 ; gain = 0.000 ; free physical = 7524 ; free virtual = 42790 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2129.957 ; gain = 30.758 ; free physical = 7524 ; free virtual = 42790 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.945 ; gain = 37.746 ; free physical = 7476 ; free virtual = 42742 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.945 ; gain = 37.746 ; free physical = 7476 ; free virtual = 42742 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7383 ; free virtual = 42649 Phase 3 Initial Routing INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2] WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7435 ; free virtual = 42701 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7429 ; free virtual = 42698 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7429 ; free virtual = 42698 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7429 ; free virtual = 42698 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7429 ; free virtual = 42698 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7428 ; free virtual = 42697 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2004.168 ; gain = 458.203 ; free physical = 7367 ; free virtual = 42644 Phase 1.3 Build Placer Netlist Model Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7362 ; free virtual = 42640 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7359 ; free virtual = 42637 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7355 ; free virtual = 42634 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.000 ; gain = 57.801 ; free physical = 7392 ; free virtual = 42671 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:52 . Memory (MB): peak = 2195.789 ; gain = 96.590 ; free physical = 7391 ; free virtual = 42670 Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 7434 ; free virtual = 42707 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15b0a291a Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2055.930 ; gain = 92.668 ; free physical = 7407 ; free virtual = 42681 Loading data files... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15b0a291a Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.918 ; gain = 97.656 ; free physical = 7378 ; free virtual = 42652 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15b0a291a Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2060.918 ; gain = 97.656 ; free physical = 7378 ; free virtual = 42652 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 7356 ; free virtual = 42653 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 7275 ; free virtual = 42575 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 7264 ; free virtual = 42565 Phase 4 Rip-up And Reroute | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 7264 ; free virtual = 42565 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 7264 ; free virtual = 42565 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 7264 ; free virtual = 42565 Phase 6 Post Hold Fix | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 7264 ; free virtual = 42565 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 7294 ; free virtual = 42576 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 7294 ; free virtual = 42576 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 7290 ; free virtual = 42573 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 7288 ; free virtual = 42571 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 7287 ; free virtual = 42569 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 7316 ; free virtual = 42599 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.762 ; gain = 179.516 ; free physical = 7316 ; free virtual = 42598 INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 7271 ; free virtual = 42557 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 18806395d Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.957 ; gain = 42.668 ; free physical = 7241 ; free virtual = 42527 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Loading data files... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18806395d Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2075.945 ; gain = 50.656 ; free physical = 7191 ; free virtual = 42478 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18806395d Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2075.945 ; gain = 50.656 ; free physical = 7189 ; free virtual = 42476 Number of Nodes with overlaps = 0 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.168 ; gain = 458.203 ; free physical = 7054 ; free virtual = 42344 Phase 1.4 Constrain Clocks/Macros Writing XDEF routing. Phase 2 Router Initialization | Checksum: df19d8a1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 7062 ; free virtual = 42352 Phase 3 Initial Routing Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2195.789 ; gain = 0.000 ; free physical = 7069 ; free virtual = 42360 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.168 ; gain = 458.203 ; free physical = 7044 ; free virtual = 42335 Running DRC as a precondition to command write_bitstream Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 7054 ; free virtual = 42346 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.1 Global Iteration 0 | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 7052 ; free virtual = 42344 Phase 4 Rip-up And Reroute | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 7051 ; free virtual = 42342 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 7051 ; free virtual = 42342 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 7049 ; free virtual = 42341 Phase 6 Post Hold Fix | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 7047 ; free virtual = 42339 Phase 7 Route finalize Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.168 ; gain = 458.203 ; free physical = 7047 ; free virtual = 42338 Phase 2 Global Placement Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 7028 ; free virtual = 42320 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.250 ; gain = 66.961 ; free physical = 7029 ; free virtual = 42316 Phase 9 Depositing Routes INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.250 ; gain = 66.961 ; free physical = 7015 ; free virtual = 42285 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.250 ; gain = 66.961 ; free physical = 7051 ; free virtual = 42321 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2131.039 ; gain = 137.766 ; free physical = 7049 ; free virtual = 42318 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2131.039 ; gain = 0.000 ; free physical = 6928 ; free virtual = 42201 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 6903 ; free virtual = 42176 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 6446 ; free virtual = 41716 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 6441 ; free virtual = 41712 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 6355 ; free virtual = 41625 Phase 3.2 Commit Most Macros & LUTRAMs WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 6351 ; free virtual = 41621 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 6289 ; free virtual = 41559 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 6351 ; free virtual = 41622 Phase 3.4 Pipeline Register Optimization Loading data files... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 6324 ; free virtual = 41594 Phase 3.5 Small Shape Detail Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 6092 ; free virtual = 41362 Phase 1.3 Build Placer Netlist Model INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:16] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5941 ; free virtual = 41211 Phase 3.6 Re-assign LUT pins WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5970 ; free virtual = 41241 Phase 3.7 Pipeline Register Optimization Loading site data... Loading data files... Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5971 ; free virtual = 41247 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 5953 ; free virtual = 41224 --------------------------------------------------------------------------------- Loading route data... Processing options... Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5954 ; free virtual = 41224 Creating bitmap... Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 5929 ; free virtual = 41200 --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5932 ; free virtual = 41203 Phase 4.2 Post Placement Cleanup Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 5877 ; free virtual = 41147 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 5880 ; free virtual = 41151 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 5874 ; free virtual = 41145 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5869 ; free virtual = 41140 Phase 4.3 Placer Reporting INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5827 ; free virtual = 41098 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5827 ; free virtual = 41098 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5777 ; free virtual = 41048 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.211 ; gain = 546.246 ; free physical = 5746 ; free virtual = 41017 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.211 ; gain = 624.949 ; free physical = 5746 ; free virtual = 41016 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5708 ; free virtual = 40979 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 5610 ; free virtual = 40881 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Loading route data... Processing options... Creating bitmap... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 5564 ; free virtual = 40835 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 5592 ; free virtual = 40863 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:14 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 5602 ; free virtual = 40872 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 5601 ; free virtual = 40872 Phase 2 Final Placement Cleanup INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5583 ; free virtual = 40854 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5574 ; free virtual = 40845 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 5577 ; free virtual = 40848 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Starting Routing Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5601 ; free virtual = 40871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 5595 ; free virtual = 40866 --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5595 ; free virtual = 40866 --------------------------------------------------------------------------------- 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 5594 ; free virtual = 40865 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5590 ; free virtual = 40861 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5583 ; free virtual = 40854 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5580 ; free virtual = 40851 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5584 ; free virtual = 40855 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 5582 ; free virtual = 40852 Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1546.863 ; gain = 0.000 ; free physical = 5754 ; free virtual = 41029 Creating bitstream... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1546.863 ; gain = 0.000 ; free physical = 5754 ; free virtual = 41029 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:31:38 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2454.871 ; gain = 343.105 ; free physical = 5501 ; free virtual = 40776 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:31:38 2019... Writing bitstream ./design.bit... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Loading site data... touch build/specimen_016/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_020 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Creating bitstream... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 6657 ; free virtual = 41935 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 6587 ; free virtual = 41866 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading route data... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Processing options... Creating bitmap... WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6527 ; free virtual = 41806 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:31:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2535.367 ; gain = 339.105 ; free physical = 6463 ; free virtual = 41742 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:31:42 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7497 ; free virtual = 42775 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7495 ; free virtual = 42774 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Creating bitstream... touch build/specimen_013/OK --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7493 ; free virtual = 42772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_017 Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7494 ; free virtual = 42773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7494 ; free virtual = 42773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7494 ; free virtual = 42772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7494 ; free virtual = 42772 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7493 ; free virtual = 42772 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 7495 ; free virtual = 42774 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:31:48 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2454.867 ; gain = 344.105 ; free physical = 7923 ; free virtual = 43211 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:31:48 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_017/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_017 Phase 1 Build RT Design | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 8778 ; free virtual = 44066 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 8746 ; free virtual = 44034 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 8746 ; free virtual = 44034 Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 781ffd05 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8784 ; free virtual = 44079 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8866 ; free virtual = 44163 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8864 ; free virtual = 44161 Phase 4 Rip-up And Reroute | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8865 ; free virtual = 44162 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8866 ; free virtual = 44164 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8869 ; free virtual = 44166 Phase 6 Post Hold Fix | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8870 ; free virtual = 44167 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 9070 ; free virtual = 44367 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 9072 ; free virtual = 44369 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 9078 ; free virtual = 44375 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 9119 ; free virtual = 44416 Routing Is Done.INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 9120 ; free virtual = 44417 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 9112 ; free virtual = 44411 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:31:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2532.895 ; gain = 337.105 ; free physical = 9054 ; free virtual = 44351 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:31:52 2019... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_018 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 10ee63a33 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 10051 ; free virtual = 45349 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10ee63a33 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 9981 ; free virtual = 45279 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10ee63a33 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 9980 ; free virtual = 45279 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 9989 ; free virtual = 45287 Phase 3 Initial Routing INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:31:54 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2469.145 ; gain = 338.105 ; free physical = 9989 ; free virtual = 45287 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:31:54 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10000 ; free virtual = 45298 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10013 ; free virtual = 45311 Phase 4 Rip-up And Reroute | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10013 ; free virtual = 45311 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10014 ; free virtual = 45312 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10014 ; free virtual = 45312 Phase 6 Post Hold Fix | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10016 ; free virtual = 45314 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 10090 ; free virtual = 45388 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 10169 ; free virtual = 45467 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 10403 ; free virtual = 45702 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 10651 ; free virtual = 45949 Routing Is Done. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 10700 ; free virtual = 45998 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 10749 ; free virtual = 46047 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Writing placer database... Bitstream size: 4243411 bytes Writing XDEF routing. Config size: 1060815 words Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 11009 ; free virtual = 46308 Number of configuration frames: 9996 DONE Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' touch build/specimen_015/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1545.949 ; gain = 0.000 ; free physical = 10747 ; free virtual = 46047 Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 15 #of bits: 43412 #of tags: 700 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_018 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.51 . Memory (MB): peak = 1545.949 ; gain = 0.000 ; free physical = 10716 ; free virtual = 46016 Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:10 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 10503 ; free virtual = 45808 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 10446 ; free virtual = 45752 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.395 ; gain = 505.531 ; free physical = 10270 ; free virtual = 45575 Phase 1.3 Build Placer Netlist Model INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1552.863 ; gain = 0.000 ; free physical = 10249 ; free virtual = 45554 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.54 . Memory (MB): peak = 1552.863 ; gain = 0.000 ; free physical = 10241 ; free virtual = 45546 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9738 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 505.531 ; free physical = 9820 ; free virtual = 45126 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 505.531 ; free physical = 9710 ; free virtual = 45015 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 505.531 ; free physical = 9763 ; free virtual = 45068 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 505.531 ; free physical = 9730 ; free virtual = 45035 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9782 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 505.531 ; free physical = 9720 ; free virtual = 45025 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 9721 ; free virtual = 45026 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Loading site data... Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Creating bitstream... Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 9476 ; free virtual = 44786 --------------------------------------------------------------------------------- Creating bitstream... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9850 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9892 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9289 ; free virtual = 44599 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9310 ; free virtual = 44620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9309 ; free virtual = 44619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9303 ; free virtual = 44613 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 9051 ; free virtual = 44365 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:32:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 9241 ; free virtual = 44555 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:32:15 2019... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2130.645 ; gain = 38.434 ; free physical = 9227 ; free virtual = 44541 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.633 ; gain = 44.422 ; free physical = 9251 ; free virtual = 44565 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.633 ; gain = 44.422 ; free physical = 9252 ; free virtual = 44566 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 9326 ; free virtual = 44640 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } touch build/specimen_018/OK ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_019 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 10046 ; free virtual = 45360 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9971 ; free virtual = 45285 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9967 ; free virtual = 45281 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9968 ; free virtual = 45282 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9969 ; free virtual = 45283 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9970 ; free virtual = 45284 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9971 ; free virtual = 45285 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9959 ; free virtual = 45273 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9962 ; free virtual = 45276 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9960 ; free virtual = 45274 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.688 ; gain = 63.477 ; free physical = 9994 ; free virtual = 45308 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2194.477 ; gain = 102.266 ; free physical = 9993 ; free virtual = 45307 Writing placer database... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2004.152 ; gain = 458.203 ; free physical = 10025 ; free virtual = 45347 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:32:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2452.871 ; gain = 342.105 ; free physical = 9837 ; free virtual = 45168 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:32:19 2019... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10032 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_019/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_019 Phase 1 Build RT Design | Checksum: 118b3be9c Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2133.074 ; gain = 48.668 ; free physical = 10623 ; free virtual = 45959 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:16] INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 118b3be9c Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2141.062 ; gain = 56.656 ; free physical = 10486 ; free virtual = 45826 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 118b3be9c Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2141.062 ; gain = 56.656 ; free physical = 10481 ; free virtual = 45821 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:7] Writing XDEF routing. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:2] Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.477 ; gain = 0.000 ; free physical = 10454 ; free virtual = 45795 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2004.152 ; gain = 458.203 ; free physical = 10500 ; free virtual = 45846 Phase 1.4 Constrain Clocks/Macros Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 10532 ; free virtual = 45881 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10544 ; free virtual = 45866 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.152 ; gain = 458.203 ; free physical = 10544 ; free virtual = 45867 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10582 ; free virtual = 45905 Phase 3 Initial Routing Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.152 ; gain = 458.203 ; free physical = 10550 ; free virtual = 45878 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10471 ; free virtual = 45798 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 10466 ; free virtual = 45793 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10485 ; free virtual = 45808 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4.1 Global Iteration 0 | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10502 ; free virtual = 45824 Phase 4 Rip-up And Reroute | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10506 ; free virtual = 45828 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10506 ; free virtual = 45829 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10506 ; free virtual = 45829 Phase 6 Post Hold Fix | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10505 ; free virtual = 45827 Phase 7 Route finalize No constraint files found. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0--------------------------------------------------------------------------------- Number of Unrouted Nets = Start Cross Boundary and Area Optimization 0 --------------------------------------------------------------------------------- Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10520 ; free virtual = 45843 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10537 ; free virtual = 45859 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10531 ; free virtual = 45853 Phase 8 Verifying routed nets Verification completed successfully --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10523 ; free virtual = 45845 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 8 Verifying routed nets | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10517 ; free virtual = 45839 Phase 9 Depositing Routes Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 10450 ; free virtual = 45772 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 145a2d7e1 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10369 ; free virtual = 45691 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2176.992 ; gain = 92.586 ; free physical = 10411 ; free virtual = 45734 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2215.781 ; gain = 163.391 ; free physical = 10410 ; free virtual = 45732 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 10400 ; free virtual = 45722 --------------------------------------------------------------------------------- Writing placer database... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10393 ; free virtual = 45716 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10393 ; free virtual = 45716 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10392 ; free virtual = 45716 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10392 ; free virtual = 45716 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 10392 ; free virtual = 45715 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10393 ; free virtual = 45716 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10393 ; free virtual = 45716 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10393 ; free virtual = 45716 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10393 ; free virtual = 45717 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 10395 ; free virtual = 45719 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 10261 ; free virtual = 45594 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:72] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:312] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:384] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:408] No constraint files found. WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:432] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:432] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:30] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:456] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:35] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:456] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:35] Detailed RTL Component Info : WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:40] +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:475] Start RTL Hierarchical Component Statistics WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:40] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:45] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:50] Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:50] Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:55] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:504] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:60] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:504] --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:65] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:528] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:70] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:528] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:75] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:552] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:80] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:552] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:85] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:576] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:90] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:576] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:100] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:600] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:100] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:600] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:110] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:624] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:115] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:624] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:648] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:125] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:648] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:130] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:672] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:135] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:672] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:140] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:691] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:696] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:145] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:696] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:150] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:720] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:155] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:720] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:165] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:744] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:170] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:744] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:175] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:768] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:180] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:768] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:185] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:792] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:190] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:792] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:195] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:811] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:816] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:205] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:840] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:210] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:840] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:220] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:864] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:225] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:864] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:230] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:888] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:235] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:888] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:912] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:245] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:912] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:250] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:936] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:255] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:936] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:260] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:960] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:265] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:960] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:270] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:979] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:984] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:275] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:984] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:280] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1008] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:285] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1008] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:295] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1032] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:300] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1032] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:305] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1056] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:310] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1056] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:315] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:320] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:325] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1099] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:330] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1104] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:335] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1128] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:340] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:350] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1152] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:355] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1152] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1176] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:365] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1176] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:370] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:375] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1224] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1368] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1392] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1416] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1464] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1488] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1512] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1536] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1560] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 10195 ; free virtual = 45530 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 10203 ; free virtual = 45540 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 10210 ; free virtual = 45551 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 10178 ; free virtual = 45522 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 10166 ; free virtual = 45511 Phase 3.5 Small Shape Detail Placement Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2215.781 ; gain = 0.000 ; free physical = 10064 ; free virtual = 45415 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2215.781 ; gain = 0.000 ; free physical = 10008 ; free virtual = 45333 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 10006 ; free virtual = 45331 Phase 1.4 Constrain Clocks/Macros INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 10025 ; free virtual = 45350 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 10020 ; free virtual = 45345 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 9976 ; free virtual = 45302 Phase 2 Final Placement Cleanup WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:16] Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9967 ; free virtual = 45293 Phase 3.6 Re-assign LUT pins Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 9963 ; free virtual = 45289 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 499.531 ; free physical = 9968 ; free virtual = 45293 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9964 ; free virtual = 45289 Phase 3.7 Pipeline Register Optimization 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 9959 ; free virtual = 45284 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:2] Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 9929 ; free virtual = 45255 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9921 ; free virtual = 45251 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9954 ; free virtual = 45280 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 9889 ; free virtual = 45220 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 9887 ; free virtual = 45219 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9881 ; free virtual = 45213 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9829 ; free virtual = 45155 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 9876 ; free virtual = 45202 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9848 ; free virtual = 45174 Phase 4.2 Post Placement Cleanup No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9712 ; free virtual = 45038 --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9706 ; free virtual = 45032 Phase 4.3 Placer Reporting Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9766 ; free virtual = 45092 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9763 ; free virtual = 45089 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9763 ; free virtual = 45089 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9741 ; free virtual = 45066 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9792 ; free virtual = 45118 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.199 ; gain = 554.250 ; free physical = 9783 ; free virtual = 45109 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.199 ; gain = 632.953 ; free physical = 9783 ; free virtual = 45109 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Routing Task INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:72] INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9648 ; free virtual = 44974 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9644 ; free virtual = 44970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9659 ; free virtual = 44985 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9658 ; free virtual = 44984 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9658 ; free virtual = 44984 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9658 ; free virtual = 44984 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9658 ; free virtual = 44984 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9660 ; free virtual = 44986 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 9662 ; free virtual = 44988 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 9663 ; free virtual = 44989 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9063 ; free virtual = 44410 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9046 ; free virtual = 44393 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9043 ; free virtual = 44371 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8991 ; free virtual = 44319 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8815 ; free virtual = 44163 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8811 ; free virtual = 44159 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 8817 ; free virtual = 44145 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8816 ; free virtual = 44143 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 8814 ; free virtual = 44142 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8851 ; free virtual = 44179 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: Helper process launched with PID 11013 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8848 ; free virtual = 44176 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8850 ; free virtual = 44178 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8851 ; free virtual = 44179 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8850 ; free virtual = 44177 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 8851 ; free virtual = 44179 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: Helper process launched with PID 11062 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1468.250 ; gain = 385.359 ; free physical = 8739 ; free virtual = 44071 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 8744 ; free virtual = 44082 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 8740 ; free virtual = 44089 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 8725 ; free virtual = 44078 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 8685 ; free virtual = 44020 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:32:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.582 ; gain = 338.105 ; free physical = 8678 ; free virtual = 44023 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:32:49 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_020 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 9578 ; free virtual = 44911 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 9577 ; free virtual = 44910 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: fa6cad5b Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2136.078 ; gain = 51.668 ; free physical = 9466 ; free virtual = 44800 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: fa6cad5b Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.605 ; gain = 61.195 ; free physical = 9168 ; free virtual = 44505 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: fa6cad5b Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.605 ; gain = 61.195 ; free physical = 9168 ; free virtual = 44506 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 9135 ; free virtual = 44469 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Loading site data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 19ba50c22 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9114 ; free virtual = 44449 Phase 3 Initial Routing Loading route data... Processing options... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 9064 ; free virtual = 44399 --------------------------------------------------------------------------------- Creating bitmap... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9058 ; free virtual = 44393 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9053 ; free virtual = 44388 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9049 ; free virtual = 44384 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9049 ; free virtual = 44384 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9048 ; free virtual = 44382 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9046 ; free virtual = 44381 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 9045 ; free virtual = 44380 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Number of Nodes with overlaps = 0 No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9026 ; free virtual = 44361 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9021 ; free virtual = 44356 Phase 4 Rip-up And Reroute | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9020 ; free virtual = 44355 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9017 ; free virtual = 44352 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter --------------------------------------------------------------------------------- Phase 6.1 Hold Fix Iter | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9018 ; free virtual = 44353 Phase 6 Post Hold Fix | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9019 ; free virtual = 44353 Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 9018 ; free virtual = 44353 --------------------------------------------------------------------------------- Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 9002 ; free virtual = 44337 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9006 ; free virtual = 44341 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9002 ; free virtual = 44337 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 19ba50c22 Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 8977 ; free virtual = 44312 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2198.535 ; gain = 114.125 ; free physical = 9021 ; free virtual = 44356 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:48 . Memory (MB): peak = 2237.324 ; gain = 184.930 ; free physical = 9021 ; free virtual = 44356 Writing placer database... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 8953 ; free virtual = 44293 --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 8998 ; free virtual = 44339 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1752] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1776] Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8864 ; free virtual = 44208 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1800] --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1920] --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2016] --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2376] --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 8824 ; free virtual = 44177 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:470] Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:480] Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.68 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 8798 ; free virtual = 44154 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing XDEF routing. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8797 ; free virtual = 44158 --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 1353.074 ; gain = 257.152 ; free physical = 8802 ; free virtual = 44163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8802 ; free virtual = 44164 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2237.324 ; gain = 0.000 ; free physical = 8800 ; free virtual = 44163 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8795 ; free virtual = 44159 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8794 ; free virtual = 44158 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8793 ; free virtual = 44156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8792 ; free virtual = 44156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8792 ; free virtual = 44156 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.082 ; gain = 255.168 ; free physical = 8791 ; free virtual = 44155 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1351.090 ; gain = 255.168 ; free physical = 8793 ; free virtual = 44157 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2237.324 ; gain = 0.000 ; free physical = 8788 ; free virtual = 44126 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1361.105 ; gain = 265.184 ; free physical = 8763 ; free virtual = 44101 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1361.105 ; gain = 265.184 ; free physical = 8706 ; free virtual = 44045 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:2] Creating bitstream... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:46 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8873 ; free virtual = 44211 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:21 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8830 ; free virtual = 44169 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:21 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8797 ; free virtual = 44136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:21 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 8796 ; free virtual = 44135 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8776 ; free virtual = 44115 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8772 ; free virtual = 44111 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8751 ; free virtual = 44090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8745 ; free virtual = 44083 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8740 ; free virtual = 44079 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8735 ; free virtual = 44074 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8733 ; free virtual = 44072 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 8730 ; free virtual = 44069 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1369.090 ; gain = 273.160 ; free physical = 8731 ; free virtual = 44069 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 8836 ; free virtual = 44179 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2] INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8601 ; free virtual = 43946 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:33:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:44 . Memory (MB): peak = 2605.941 ; gain = 390.160 ; free physical = 8404 ; free virtual = 43768 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:33:12 2019... INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8802 ; free virtual = 44145 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 8936 ; free virtual = 44279 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.441 ; gain = 0.000 ; free physical = 9439 ; free virtual = 44782 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_020 Loading data files... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9224 ; free virtual = 44568 --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9267 ; free virtual = 44617 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.156 ; gain = 455.203 ; free physical = 9231 ; free virtual = 44581 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9212 ; free virtual = 44562 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9159 ; free virtual = 44509 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9153 ; free virtual = 44503 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9135 ; free virtual = 44485 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9130 ; free virtual = 44480 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9120 ; free virtual = 44470 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9114 ; free virtual = 44463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9108 ; free virtual = 44457 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9102 ; free virtual = 44451 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 9103 ; free virtual = 44453 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 9019 ; free virtual = 44368 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11402 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2004.156 ; gain = 455.203 ; free physical = 8836 ; free virtual = 44185 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2004.156 ; gain = 455.203 ; free physical = 8723 ; free virtual = 44073 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2004.156 ; gain = 455.203 ; free physical = 8697 ; free virtual = 44047 Phase 2 Global Placement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 8643 ; free virtual = 43993 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 16930dc89 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2133.078 ; gain = 48.668 ; free physical = 8589 ; free virtual = 43939 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 16930dc89 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 8502 ; free virtual = 43852 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 16930dc89 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 8500 ; free virtual = 43850 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8483 ; free virtual = 43833 --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8465 ; free virtual = 43815 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 8449 ; free virtual = 43799 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1065a9434 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8437 ; free virtual = 43786 Phase 3 Initial Routing Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8437 ; free virtual = 43787 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1065a9434 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8432 ; free virtual = 43782 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1065a9434 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8428 ; free virtual = 43777 Phase 4 Rip-up And Reroute | Checksum: 1065a9434 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8425 ; free virtual = 43775 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1065a9434 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8421 ; free virtual = 43771 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1065a9434 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8418 ; free virtual = 43768 Phase 6 Post Hold Fix | Checksum: 1065a9434 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8403 ; free virtual = 43753 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8403 ; free virtual = 43752 Phase 3.2 Commit Most Macros & LUTRAMs Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8380 ; free virtual = 43730 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8376 ; free virtual = 43726 Phase 9 Depositing Routes Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.426 ; gain = 30.227 ; free physical = 8374 ; free virtual = 43724 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.414 ; gain = 36.215 ; free physical = 8332 ; free virtual = 43682 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.414 ; gain = 36.215 ; free physical = 8332 ; free virtual = 43682 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8330 ; free virtual = 43680 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8329 ; free virtual = 43678 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization Phase 9 Depositing Routes | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8328 ; free virtual = 43678 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 8372 ; free virtual = 43722 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:54 . Memory (MB): peak = 2217.785 ; gain = 165.391 ; free physical = 8372 ; free virtual = 43722 Loading site data... --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8353 ; free virtual = 43703 Phase 3.4 Pipeline Register Optimization Writing placer database... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading route data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8325 ; free virtual = 43677 Phase 3 Initial Routing Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8320 ; free virtual = 43673 Phase 3.5 Small Shape Detail Placement Processing options... Creating bitmap... INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8309 ; free virtual = 43664 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8308 ; free virtual = 43663 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8308 ; free virtual = 43663 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8308 ; free virtual = 43663 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8308 ; free virtual = 43663 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8308 ; free virtual = 43663 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8318 ; free virtual = 43673 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8320 ; free virtual = 43675 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8324 ; free virtual = 43680 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.469 ; gain = 55.270 ; free physical = 8360 ; free virtual = 43716 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:52 . Memory (MB): peak = 2194.258 ; gain = 94.059 ; free physical = 8360 ; free virtual = 43716 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:14 . Memory (MB): peak = 1476.848 ; gain = 393.961 ; free physical = 8381 ; free virtual = 43737 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8378 ; free virtual = 43735 --------------------------------------------------------------------------------- Writing placer database... Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8371 ; free virtual = 43729 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8358 ; free virtual = 43718 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8354 ; free virtual = 43715 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8351 ; free virtual = 43713 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8348 ; free virtual = 43710 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8339 ; free virtual = 43701 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8336 ; free virtual = 43699 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 8337 ; free virtual = 43700 INFO: [Project 1-571] Translating synthesized netlist Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8246 ; free virtual = 43615 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8237 ; free virtual = 43610 Phase 3.7 Pipeline Register Optimization Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 8230 ; free virtual = 43605 Phase 1.4 Constrain Clocks/Macros Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8227 ; free virtual = 43603 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8219 ; free virtual = 43599 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 8219 ; free virtual = 43598 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8206 ; free virtual = 43589 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 8206 ; free virtual = 43590 Phase 2 Global Placement Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8223 ; free virtual = 43609 Phase 4.3 Placer Reporting report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8171 ; free virtual = 43560 Phase 4.4 Final Placement Cleanup Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1543.879 ; gain = 0.000 ; free physical = 8178 ; free virtual = 43570 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8177 ; free virtual = 43569 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.785 ; gain = 0.000 ; free physical = 8109 ; free virtual = 43508 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.94 . Memory (MB): peak = 1543.879 ; gain = 0.000 ; free physical = 8110 ; free virtual = 43508 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8102 ; free virtual = 43501 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Writing XDEF routing. INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 8217 ; free virtual = 43618 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2194.258 ; gain = 0.000 ; free physical = 8217 ; free virtual = 43619 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.203 ; gain = 551.250 ; free physical = 8154 ; free virtual = 43556 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 2100.203 ; gain = 631.953 ; free physical = 8147 ; free virtual = 43550 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: placer_checks Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 8077 ; free virtual = 43480 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2217.785 ; gain = 0.000 ; free physical = 8140 ; free virtual = 43516 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2194.258 ; gain = 0.000 ; free physical = 8151 ; free virtual = 43505 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1549.953 ; gain = 0.000 ; free physical = 8132 ; free virtual = 43486 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1549.953 ; gain = 0.000 ; free physical = 8200 ; free virtual = 43555 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8183 ; free virtual = 43538 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8119 ; free virtual = 43473 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8020 ; free virtual = 43374 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8048 ; free virtual = 43403 Phase 3.4 Pipeline Register Optimization INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8035 ; free virtual = 43389 Phase 3.5 Small Shape Detail Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:19 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 8021 ; free virtual = 43376 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Creating bitstream... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8029 ; free virtual = 43383 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7978 ; free virtual = 43332 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7943 ; free virtual = 43297 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7878 ; free virtual = 43232 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:16] Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7852 ; free virtual = 43206 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7798 ; free virtual = 43152 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7780 ; free virtual = 43135 Phase 4.4 Final Placement Cleanup WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:7] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:2] Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7817 ; free virtual = 43171 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7814 ; free virtual = 43173 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:21 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7832 ; free virtual = 43187 --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7863 ; free virtual = 43217 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.199 ; gain = 630.953 ; free physical = 7866 ; free virtual = 43221 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Writing bitstream ./design.bit... Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1554.863 ; gain = 0.000 ; free physical = 7784 ; free virtual = 43142 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7786 ; free virtual = 43142 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 7786 ; free virtual = 43142 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.74 . Memory (MB): peak = 1554.863 ; gain = 0.000 ; free physical = 7806 ; free virtual = 43166 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13024 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 7725 ; free virtual = 43084 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 13e11bf6c Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 7631 ; free virtual = 42990 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13e11bf6c Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 7609 ; free virtual = 42968 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13e11bf6c Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 7605 ; free virtual = 42964 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b4599df1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7565 ; free virtual = 42924 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7526 ; free virtual = 42885 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7530 ; free virtual = 42889 Phase 4 Rip-up And Reroute | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7530 ; free virtual = 42889 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7530 ; free virtual = 42889 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7530 ; free virtual = 42889 Phase 6 Post Hold Fix | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7530 ; free virtual = 42889 Phase 7 Route finalize Loading data files... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7520 ; free virtual = 42879 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7518 ; free virtual = 42877 Phase 9 Depositing Routes INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:33:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 9 Depositing Routes | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7520 ; free virtual = 42879 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7556 ; free virtual = 42915 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 7557 ; free virtual = 42916 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:45 . Memory (MB): peak = 2608.984 ; gain = 371.660 ; free physical = 7563 ; free virtual = 42922 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:33:45 2019... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 7619 ; free virtual = 42978 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8387 ; free virtual = 43746 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8330 ; free virtual = 43689 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8268 ; free virtual = 43626 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7926 ; free virtual = 43285 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7939 ; free virtual = 43298 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7927 ; free virtual = 43285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7932 ; free virtual = 43291 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7932 ; free virtual = 43291 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7931 ; free virtual = 43290 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7931 ; free virtual = 43290 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7928 ; free virtual = 43287 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 7928 ; free virtual = 43286 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading data files... INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 7658 ; free virtual = 43017 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 7403 ; free virtual = 42762 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.367 ; gain = 0.000 ; free physical = 7264 ; free virtual = 42622 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 7263 ; free virtual = 42622 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2] Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1552.859 ; gain = 0.000 ; free physical = 7197 ; free virtual = 42556 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1552.859 ; gain = 0.000 ; free physical = 7152 ; free virtual = 42511 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Loading site data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.156 ; gain = 453.203 ; free physical = 7076 ; free virtual = 42435 Phase 1.3 Build Placer Netlist Model Writing bitstream ./design.bit... Loading route data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.410 ; gain = 508.531 ; free physical = 6989 ; free virtual = 42351 Phase 1.3 Build Placer Netlist Model Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.156 ; gain = 453.203 ; free physical = 6822 ; free virtual = 42185 Phase 1.4 Constrain Clocks/Macros INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:34:01 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.363 ; gain = 338.105 ; free physical = 6821 ; free virtual = 42184 Loading site data... INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:34:01 2019... Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.156 ; gain = 453.203 ; free physical = 6851 ; free virtual = 42213 INFO: [Timing 38-35] Done setting XDC timing constraints. Loading route data... Processing options... Creating bitmap... Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.156 ; gain = 453.203 ; free physical = 7863 ; free virtual = 43226 Phase 2 Global Placement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_016/OK INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 7833 ; free virtual = 43196 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.410 ; gain = 508.531 ; free physical = 7815 ; free virtual = 43178 Phase 1.4 Constrain Clocks/Macros INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.410 ; gain = 508.531 ; free physical = 7849 ; free virtual = 43212 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:47 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 7850 ; free virtual = 43213 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.410 ; gain = 508.531 ; free physical = 7850 ; free virtual = 43213 Phase 2 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.410 ; gain = 508.531 ; free physical = 7840 ; free virtual = 43203 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.410 ; gain = 508.531 ; free physical = 7835 ; free virtual = 43198 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 2052.410 ; gain = 575.562 ; free physical = 7814 ; free virtual = 43176 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 7823 ; free virtual = 43186 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 7818 ; free virtual = 43181 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 7818 ; free virtual = 43181 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 7819 ; free virtual = 43182 Phase 1.3 Build Placer Netlist Model Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 7818 ; free virtual = 43181 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 7847 ; free virtual = 43210 Phase 3.3 Area Swap Optimization Writing bitstream ./design.bit... Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 7839 ; free virtual = 43205 Phase 3.4 Pipeline Register Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 7923 ; free virtual = 43290 Phase 3.5 Small Shape Detail Placement Creating bitstream... Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2] Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8116 ; free virtual = 43483 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8130 ; free virtual = 43501 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8118 ; free virtual = 43495 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8106 ; free virtual = 43490 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Writing bitstream ./design.bit... Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8096 ; free virtual = 43487 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8234 ; free virtual = 43625 Phase 4.3 Placer Reporting --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 8397 ; free virtual = 43770 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8449 ; free virtual = 43822 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8488 ; free virtual = 43861 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8478 ; free virtual = 43855 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 8516 ; free virtual = 43908 Phase 1.4 Constrain Clocks/Macros Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 549.250 ; free physical = 8514 ; free virtual = 43907 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 8514 ; free virtual = 43906 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 8510 ; free virtual = 43903 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 8489 ; free virtual = 43882 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 8440 ; free virtual = 43832 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:34:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 8448 ; free virtual = 43841 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:34:11 2019... Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 8460 ; free virtual = 43852 --------------------------------------------------------------------------------- 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 8501 ; free virtual = 43874 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 8501 ; free virtual = 43874 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 8506 ; free virtual = 43879 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Device 21-403] Loading part xc7z020clg400-1 Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_020/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 1436 #of tags: 192 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:34:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:42 . Memory (MB): peak = 2606.945 ; gain = 389.160 ; free physical = 9313 ; free virtual = 44685 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:34:14 2019... Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_016/OK --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 10012 ; free virtual = 45385 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 10011 ; free virtual = 45383 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2129.633 ; gain = 29.430 ; free physical = 9976 ; free virtual = 45348 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.621 ; gain = 35.418 ; free physical = 9943 ; free virtual = 45316 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.621 ; gain = 35.418 ; free physical = 9943 ; free virtual = 45316 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9921 ; free virtual = 45294 Phase 3 Initial Routing No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9906 ; free virtual = 45279 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9901 ; free virtual = 45274 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9901 ; free virtual = 45274 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9901 ; free virtual = 45274 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9900 ; free virtual = 45273 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9899 ; free virtual = 45272 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9893 ; free virtual = 45266 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9890 ; free virtual = 45263 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9889 ; free virtual = 45261 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.676 ; gain = 53.473 ; free physical = 9923 ; free virtual = 45296 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2192.465 ; gain = 92.262 ; free physical = 9923 ; free virtual = 45296 Writing placer database... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 9916 ; free virtual = 45290 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 9894 ; free virtual = 45268 Phase 1.3 Build Placer Netlist Model Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 9878 ; free virtual = 45255 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9781 ; free virtual = 45167 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2129.426 ; gain = 30.227 ; free physical = 9686 ; free virtual = 45077 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2135.414 ; gain = 36.215 ; free physical = 9679 ; free virtual = 45072 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2135.414 ; gain = 36.215 ; free physical = 9679 ; free virtual = 45072 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.465 ; gain = 0.000 ; free physical = 9654 ; free virtual = 45049 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9628 ; free virtual = 45024 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9629 ; free virtual = 45025 Phase 3 Initial Routing Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9629 ; free virtual = 45025 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9615 ; free virtual = 45011 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9614 ; free virtual = 45010 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9612 ; free virtual = 45009 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9632 ; free virtual = 45006 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9632 ; free virtual = 45006 Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9632 ; free virtual = 45006 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9630 ; free virtual = 45004 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 9632 ; free virtual = 45006 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9632 ; free virtual = 45005 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9632 ; free virtual = 45005 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9632 ; free virtual = 45005 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9632 ; free virtual = 45005 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9632 ; free virtual = 45005 INFO: [Project 1-571] Translating synthesized netlist Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9601 ; free virtual = 44974 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9599 ; free virtual = 44972 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9592 ; free virtual = 44966 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9625 ; free virtual = 44999 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:43 . Memory (MB): peak = 2193.258 ; gain = 94.059 ; free physical = 9615 ; free virtual = 44989 Writing placer database... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 9459 ; free virtual = 44836 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 9445 ; free virtual = 44822 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 9444 ; free virtual = 44823 Phase 2 Final Placement Cleanup Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 9435 ; free virtual = 44816 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 499.531 ; free physical = 9439 ; free virtual = 44821 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 9442 ; free virtual = 44824 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 9422 ; free virtual = 44807 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.258 ; gain = 0.000 ; free physical = 9385 ; free virtual = 44782 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 9384 ; free virtual = 44780 Phase 1.3 Build Placer Netlist Model report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Loading data files... INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 9210 ; free virtual = 44585 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 9204 ; free virtual = 44579 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 9198 ; free virtual = 44573 Phase 2 Global Placement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8992 ; free virtual = 44367 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8950 ; free virtual = 44325 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:26 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8946 ; free virtual = 44321 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:26 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8894 ; free virtual = 44269 Phase 3.4 Pipeline Register Optimization Loading data files... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8890 ; free virtual = 44265 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8784 ; free virtual = 44159 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8767 ; free virtual = 44142 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8729 ; free virtual = 44104 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8726 ; free virtual = 44101 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8713 ; free virtual = 44088 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8703 ; free virtual = 44078 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8692 ; free virtual = 44067 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8691 ; free virtual = 44066 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8673 ; free virtual = 44048 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 8698 ; free virtual = 44073 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.195 ; gain = 623.949 ; free physical = 8698 ; free virtual = 44073 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Creating bitstream... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 169ce22cd Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2133.094 ; gain = 48.668 ; free physical = 8656 ; free virtual = 44035 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 2.1 Fix Topology Constraints | Checksum: 169ce22cd Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2143.082 ; gain = 58.656 ; free physical = 8573 ; free virtual = 43952 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 169ce22cd Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2143.082 ; gain = 58.656 ; free physical = 8573 ; free virtual = 43952 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:01:01 . Memory (MB): peak = 1476.840 ; gain = 393.945 ; free physical = 8621 ; free virtual = 44000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 178199bf5 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8555 ; free virtual = 43934 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 178199bf5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8497 ; free virtual = 43876 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 178199bf5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8497 ; free virtual = 43876 Phase 4 Rip-up And Reroute | Checksum: 178199bf5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8498 ; free virtual = 43877 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 178199bf5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8499 ; free virtual = 43879 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 178199bf5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8501 ; free virtual = 43880 Phase 6 Post Hold Fix | Checksum: 178199bf5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8500 ; free virtual = 43879 Phase 7 Route finalize Writing bitstream ./design.bit... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 178199bf5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8493 ; free virtual = 43875 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 178199bf5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8491 ; free virtual = 43874 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 178199bf5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8807 ; free virtual = 44190 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.012 ; gain = 94.586 ; free physical = 8862 ; free virtual = 44245 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:39 . Memory (MB): peak = 2217.801 ; gain = 165.391 ; free physical = 8868 ; free virtual = 44251 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing placer database... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1558.871 ; gain = 0.000 ; free physical = 8879 ; free virtual = 44266 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1558.871 ; gain = 0.000 ; free physical = 8876 ; free virtual = 44265 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:34:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:23 . Memory (MB): peak = 2531.570 ; gain = 339.105 ; free physical = 8880 ; free virtual = 44272 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:34:45 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_017/OK Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2217.801 ; gain = 0.000 ; free physical = 9906 ; free virtual = 45318 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:34 . Memory (MB): peak = 2129.430 ; gain = 30.227 ; free physical = 9939 ; free virtual = 45326 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:34 . Memory (MB): peak = 2135.418 ; gain = 36.215 ; free physical = 9880 ; free virtual = 45266 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:34 . Memory (MB): peak = 2135.418 ; gain = 36.215 ; free physical = 9880 ; free virtual = 45266 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:34:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2533.363 ; gain = 340.105 ; free physical = 9933 ; free virtual = 45319 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:34:47 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 9950 ; free virtual = 45335 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 1a0edab69 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2135.078 ; gain = 50.668 ; free physical = 10112 ; free virtual = 45498 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10361 ; free virtual = 45747 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10702 ; free virtual = 46087 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10719 ; free virtual = 46104 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10739 ; free virtual = 46125 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10777 ; free virtual = 46163 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10799 ; free virtual = 46185 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10960 ; free virtual = 46346 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10959 ; free virtual = 46345 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10958 ; free virtual = 46343 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 10993 ; free virtual = 46379 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:37 . Memory (MB): peak = 2193.262 ; gain = 94.059 ; free physical = 10994 ; free virtual = 46379 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. touch build/specimen_018/OK Phase 2.1 Fix Topology Constraints Writing placer database... Phase 2.1 Fix Topology Constraints | Checksum: 1a0edab69 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 10920 ; free virtual = 46307 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a0edab69 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 10918 ; free virtual = 46305 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 121342371 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10916 ; free virtual = 46310 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10920 ; free virtual = 46315 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10922 ; free virtual = 46317 Phase 4 Rip-up And Reroute | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10921 ; free virtual = 46317 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10920 ; free virtual = 46316 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10920 ; free virtual = 46316 Phase 6 Post Hold Fix | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10918 ; free virtual = 46315 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 121342371 Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10914 ; free virtual = 46312 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 121342371 Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10911 ; free virtual = 46309 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 121342371 Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10903 ; free virtual = 46305 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10946 ; free virtual = 46348 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:38 . Memory (MB): peak = 2218.785 ; gain = 166.391 ; free physical = 10946 ; free virtual = 46348 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.262 ; gain = 0.000 ; free physical = 10913 ; free virtual = 46329 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.785 ; gain = 0.000 ; free physical = 10834 ; free virtual = 46249 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Phase 1 Build RT Design | Checksum: 16ac86fd8 Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2135.074 ; gain = 50.668 ; free physical = 10339 ; free virtual = 45729 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 16ac86fd8 Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 10161 ; free virtual = 45551 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 16ac86fd8 Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 10148 ; free virtual = 45538 INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18e753ec2 Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9987 ; free virtual = 45377 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18e753ec2 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9987 ; free virtual = 45377 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18e753ec2 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9978 ; free virtual = 45369 Phase 4 Rip-up And Reroute | Checksum: 18e753ec2 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9984 ; free virtual = 45374 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18e753ec2 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9985 ; free virtual = 45375 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18e753ec2 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9985 ; free virtual = 45375 Phase 6 Post Hold Fix | Checksum: 18e753ec2 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9975 ; free virtual = 45366 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18e753ec2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9974 ; free virtual = 45365 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18e753ec2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9973 ; free virtual = 45363 Phase 9 Depositing Routes Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.359 ; gain = 0.000 ; free physical = 9972 ; free virtual = 45363 Phase 9 Depositing Routes | Checksum: 18e753ec2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 9967 ; free virtual = 45357 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 10003 ; free virtual = 45394 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:35 . Memory (MB): peak = 2218.781 ; gain = 166.391 ; free physical = 10000 ; free virtual = 45391 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2052.402 ; gain = 493.531 ; free physical = 9802 ; free virtual = 45208 Phase 1.3 Build Placer Netlist Model Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2218.781 ; gain = 0.000 ; free physical = 9702 ; free virtual = 45120 Loading data files... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.402 ; gain = 493.531 ; free physical = 9486 ; free virtual = 44880 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.402 ; gain = 493.531 ; free physical = 9483 ; free virtual = 44877 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.402 ; gain = 493.531 ; free physical = 9512 ; free virtual = 44905 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.402 ; gain = 493.531 ; free physical = 9513 ; free virtual = 44906 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.402 ; gain = 493.531 ; free physical = 9531 ; free virtual = 44925 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.402 ; gain = 575.562 ; free physical = 9531 ; free virtual = 44925 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2127.426 ; gain = 36.230 ; free physical = 9457 ; free virtual = 44851 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2134.414 ; gain = 43.219 ; free physical = 9426 ; free virtual = 44819 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2134.414 ; gain = 43.219 ; free physical = 9426 ; free virtual = 44819 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9435 ; free virtual = 44829 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9437 ; free virtual = 44831 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9437 ; free virtual = 44831 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9437 ; free virtual = 44831 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9437 ; free virtual = 44831 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9437 ; free virtual = 44831 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9437 ; free virtual = 44831 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 report_drc (run_mandatory_drcs) completed successfully Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9432 ; free virtual = 44826 Phase 8 Verifying routed nets INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9430 ; free virtual = 44824 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9430 ; free virtual = 44824 Starting Routing Task INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 9465 ; free virtual = 44859 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:34 . Memory (MB): peak = 2193.258 ; gain = 102.062 ; free physical = 9465 ; free virtual = 44859 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Writing placer database... Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... Creating bitstream... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2193.258 ; gain = 0.000 ; free physical = 9633 ; free virtual = 45054 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading route data... Writing bitstream ./design.bit... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:35:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 2531.867 ; gain = 338.605 ; free physical = 9801 ; free virtual = 45205 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:35:12 2019... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_019/OK Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:35:16 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:59 ; elapsed = 00:00:29 . Memory (MB): peak = 2607.961 ; gain = 390.160 ; free physical = 10645 ; free virtual = 46048 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:35:16 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. touch build/specimen_017/OK Loading data files... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:35:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:59 ; elapsed = 00:00:30 . Memory (MB): peak = 2607.945 ; gain = 389.160 ; free physical = 11646 ; free virtual = 47053 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:35:24 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_018/OK Creating bitstream... Writing bitstream ./design.bit... Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:35:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 2532.363 ; gain = 339.105 ; free physical = 13377 ; free virtual = 48792 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:35:30 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_020/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 6936 #of tags: 6650 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:35:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:56 ; elapsed = 00:00:29 . Memory (MB): peak = 2607.941 ; gain = 389.160 ; free physical = 14441 ; free virtual = 49856 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:35:32 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_019/OK Phase 1 Build RT Design | Checksum: 19e9914bc Time (s): cpu = 00:00:31 ; elapsed = 00:00:25 . Memory (MB): peak = 2134.086 ; gain = 49.668 ; free physical = 15600 ; free virtual = 51015 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 19e9914bc Time (s): cpu = 00:00:31 ; elapsed = 00:00:25 . Memory (MB): peak = 2144.074 ; gain = 59.656 ; free physical = 15568 ; free virtual = 50983 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 19e9914bc Time (s): cpu = 00:00:31 ; elapsed = 00:00:25 . Memory (MB): peak = 2144.074 ; gain = 59.656 ; free physical = 15568 ; free virtual = 50983 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 197d64bf1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15544 ; free virtual = 50959 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 197d64bf1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15549 ; free virtual = 50964 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 197d64bf1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15549 ; free virtual = 50964 Phase 4 Rip-up And Reroute | Checksum: 197d64bf1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15549 ; free virtual = 50964 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 197d64bf1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15549 ; free virtual = 50964 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 197d64bf1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15549 ; free virtual = 50964 Phase 6 Post Hold Fix | Checksum: 197d64bf1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15549 ; free virtual = 50964 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 197d64bf1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15549 ; free virtual = 50963 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 197d64bf1 Time (s): cpu = 00:00:33 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15547 ; free virtual = 50962 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 197d64bf1 Time (s): cpu = 00:00:33 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15547 ; free virtual = 50962 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:33 ; elapsed = 00:00:26 . Memory (MB): peak = 2179.004 ; gain = 94.586 ; free physical = 15591 ; free virtual = 51006 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2217.793 ; gain = 165.391 ; free physical = 15591 ; free virtual = 51006 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2217.793 ; gain = 0.000 ; free physical = 15556 ; free virtual = 50998 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:35:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:46 ; elapsed = 00:00:21 . Memory (MB): peak = 2607.953 ; gain = 390.160 ; free physical = 15371 ; free virtual = 50793 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:35:58 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_020/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 39912 #of tags: 6650 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' Makefile:116: recipe for target 'run' failed make[1]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid'